A programmable drive-sense unit (DSU) includes a drive-sense circuit operably coupled to a load, wherein the drive-sense circuit is configured to drive and simultaneously to sense the load via a single line, and produce an analog output based on the sensing the load. The programmable DSU also includes an analog to digital circuit operably coupled to the drive-sense circuit, where the analog to digital circuit is operable to generate a digital output based on the analog output and in accordance with one or more programmable operational parameters to achieve one or more of load sensing objectives associated with the sensing of the load and data processing objectives associated with the sensing of the load.

A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

A method for execution by one or more processing modules to configure a programmable drive-sense unit (DSU) includes determining one or more load sensing objectives based on sensing a load using the DSU that is configured to drive and simultaneously to sense the load via a single line. The method further includes determining one or more data processing objectives associated with sensing the load. The method further includes determining desired characteristics for the output data associated with sensing the load. The method further includes determining operational parameters for the DSU based on one or more of the load sensing objectives, the data processing objectives, and the desired characteristics for the output data. The method further includes configuring the DSU based on the operational parameters to achieve the one or more load sensing objectives.

A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

A system and method for communication of digital data includes receiving a plurality of data bits to be transmitted, and generating an output signal for transmission by a transmitter circuit. The generating includes generating a portion of the output signal comprising values of the output signal with magnitude less than a specified threshold, the specified threshold corresponding to a specified transmitter circuit maximum output power; and generating a portion of the output signal comprising a representation of values of the output signal with magnitude greater than the specified threshold.

A method for execution by one or more processing modules to configure a programmable drive-sense unit (DSU) includes determining one or more load sensing objectives based on sensing a load using the DSU that is configured to drive and simultaneously to sense the load via a single line. The method further includes determining one or more data processing objectives associated with sensing the load. The method further includes determining desired characteristics for the output data associated with sensing the load. The method further includes determining operational parameters for the DSU based on one or more of the load sensing objectives, the data processing objectives, and the desired characteristics for the output data. The method further includes configuring the DSU based on the operational parameters to achieve the one or more load sensing objectives.

A method executable by a low voltage drive circuit (LVDC) includes receiving an analog receive signal, converting the analog receive signal into analog inbound data, converting the analog inbound data into digital inbound data, filtering the digital inbound data to produce filtered digital data, sampling and holding an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value, adjusting formatting of the n-bit sampled digital data value to produce a formatted digital value, and generating a packet of received digital data from a plurality of formatted digital values.

The present disclosure relates to a digital frontend system for a radio device comprising a digital filter arranged for receiving digital quadrature signals and for filtering the digital quadrature signals and for outputting filtered quadrature signals; a conversion circuit arranged for receiving the filtered quadrature signals and for performing a rectangular to polar conversion of the filtered quadrature signals and for outputting a plurality of polar signals, characterized in that, the plurality of polar signals comprising an amplitude signal and quadrature phase signals.

An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.

Systems and methods are directed to phase modulation of polar coordinates in a transmitter of wireless signals, to achieve high transmit power levels while meeting spectral mask and EVM requirements. An input signal is mapped to a sequence of modulation frequency (e.g., O-QPSK to MSK) to generate a mapped signal. A digital frequency shaping filter is applied to the mapped signal to generate a shaped signal. An adaptive rounding algorithm is applied to the shaped signal to generate a reduced bit-width signal. A digital frequency synthesizer is applied to the reduced bit-width signal to generate an analog waveform for transmission.