An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

A transmitter circuit includes at least one transmitting signal processing device, a compensation device and a compensation value calibration device. The compensation device generates a first compensated input signal and a second compensated input signal by respectively processing input signals according to a first compensation value and a second compensation value. The transmitting signal processing device generates a first output signal and a second output signal by processing the first compensated input signal and the second compensated input signal. The compensation value calibration device receives the first output signal and the second output signal as a first feedback signal and a second feedback signal, respectively, and includes a digital signal processor. The digital signal processor determines a calibrated compensation value according to power of the first feedback signal and the second feedback signal at a predetermined frequency and the first compensation value and the second compensation value.

The demodulating apparatus includes circuits of receiving modulated radio signals coming from a plurality of transmission devices, first demodulating a first reception signal DPSK-modulated among the radio signals, modulating demodulation signals into modulation signals based on DPSK, estimating an amplitude and a phase of a propagation signal on a propagation path leading to the reception circuit from the transmission device on the basis of the radio signal and the modulation signal, first generating, based on the variables, a first simulated signal simulating the first reception signal from the modulation signal, extracting a signal obtained by cancelling the first simulated signal from the radio signals, and repeating processes of the first demodulating, the modulating, the estimating, the first generating and the extracting to such a limit as to enable the first demodulating.

The demodulating apparatus includes circuits of receiving modulated radio signals coming from a plurality of transmission devices, first demodulating a first reception signal DPSK-modulated among the radio signals, modulating demodulation signals into modulation signals based on DPSK, estimating an amplitude and a phase of a propagation signal on a propagation path leading to the reception circuit from the transmission device on the basis of the radio signal and the modulation signal, first generating, based on the variables, a first simulated signal simulating the first reception signal from the modulation signal, extracting a signal obtained by cancelling the first simulated signal from the radio signals, and repeating processes of the first demodulating, the modulating, the estimating, the first generating and the extracting to such a limit as to enable the first demodulating.

Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to the wireless protocol in the RF wireless domain. A computing device may be trained to generate coefficient data based on the operations of a wireless transceiver such that mixing input data using the coefficient data generates an approximation of the output data, as if it were processed by the wireless transceiver. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

A transmitter circuit includes at least one transmitting signal processing device, a compensation device and a compensation value calibration device. The compensation device generates a first compensated input signal and a second compensated input signal by respectively processing input signals according to a first compensation value and a second compensation value. The transmitting signal processing device generates a first output signal and a second output signal by processing the first compensated input signal and the second compensated input signal. The compensation value calibration device receives the first output signal and the second output signal as a first feedback signal and a second feedback signal, respectively, and includes a digital signal processor. The digital signal processor determines a calibrated compensation value according to power of the first feedback signal and the second feedback signal at a predetermined frequency and the first compensation value and the second compensation value.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

An aspect of the disclosure relates to a method of reducing a third-order intermodulation component at a first terminal of a transistor, including: receiving an input radio frequency (RF) signal cycling with a first frequency at a control terminal of the transistor; generating a feedback RF signal cycling at a second frequency at a second terminal of the transistor, wherein the second frequency is substantially twice the first frequency; and generating a third-order intermodulation cancellation component at the first terminal including combining the input RF signal with the feedback RF signal, wherein the third-order intermodulation cancellation component has a magnitude and phase substantially equal to and opposite a magnitude and phase of the third-order intermodulation component at the first terminal of the transistor, respectively.

An apparatus is disclosed for phase-shifting signals with a compensation circuit. In example implementations, an apparatus for phase-shifting signals includes a phase shifter having a first port and a second port. The phase shifter also includes a signal phase generator, a compensation circuit, and a vector modulator. The compensation circuit includes a first capacitor with a first capacitance and a second capacitor with a second capacitance. The first capacitance is different from the second capacitance. The signal phase generator is coupled between the first port and the compensation circuit. The vector modulator is coupled between the compensation circuit and the second port.