A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

An electronic device, includes an intelligent reflecting surface and an electronic device controller. The intelligent reflecting surface is configured to reflect all or a part of a received signal. The electronic device controller is configured to control the intelligent reflecting surface to determine a first phase of the intelligent reflecting surface to increase a relay gain of first data of the received signal, determine a second phase related to second data, and control a phase of the intelligent reflecting surface based on a sum of the first phase and the second phase to reflect the first data and the second data to a receiving device by beamforming.

A method for demodulating a multiplexed stereophonic signal, the signal including a signal called the sum signal, a signal called the difference signal, and a pilot signal, the method including the following steps: removing the pilot frequency from the multiplexed stereophonic signal, the resulting signal being called the pilotless signal, and subtracting the sum signal from the pilotless signal.

Techniques are provided for the generation of a calibration signal for use on an analog to digital converter (ADC). A system implementing the techniques according to an embodiment includes a calibration signal generator configured to generate a calibration tone, located in a first frequency band, in response to a calibration enable signal. The system also includes a signal summing circuit configured to generate an ADC input signal as a sum of a received signal and the calibration tone. The received signal is located in a second frequency band. The system further includes an ADC circuit configured to convert the ADC input signal to a baseband digital output signal and to perform self-calibration, based on the calibration tone, in response to the calibration enable signal. The frequency bands and the amplitude of the calibration tone are chosen to reduce interference between the received signal and the calibration tone.

A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

The present disclosure provides a method and a system to estimate LO leakage and quadrature error parameters for a transmitter RF front end, such as a direct up-conversion transmitter RF front end, in a joint fashion. The proposed method utilizes a PN sequence inserted at the transmitter baseband. At the observation receiver side, an RX accumulator is implemented to sum receiver signals to take advantage of a despreading gain using the same PN sequence from transmitter side. Through the despreading process, the receiver-transmitter channel may be estimated and used to extract the quadrature error parameters. The estimated channel may also be used to eliminate user data interference presented within the RX accumulator output, which may further be used to compute the LO leakage.

A method for processing an FM stereo signal. The FM stereo signal is digitized and divided into overlapping blocks, which are transformed into the frequency domain. Individual spectral lines of the difference signal are lowered if these have a higher magnitude than the respective spectral lines of the sum signal. The sum and difference signals are then transformed back.

A method for demodulating a multiplexed stereophonic signal, the signal including a signal called the sum signal, a signal called the difference signal, and a pilot signal, the method including the following steps: removing the pilot frequency from the multiplexed stereophonic signal, the resulting signal being called the pilotless signal, and subtracting the sum signal from the pilotless signal.

Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.

A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.