The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A method for reducing distortions of a radio frequency (RF) system includes configuring a plurality of mixers to convert between a plurality of phase signals and a plurality of RF signals, configuring a first mixer of the plurality of mixers to operate in a six-phase operating mode to reduce the distortions of the RF system, and configuring a second mixer of the plurality of mixers to operate in a three-phase operating mode to reduce power consumption of the RF system.

A method for reducing distortions of a radio frequency (RF) system includes configuring a plurality of mixers to convert between a plurality of phase signals and a plurality of RF signals, configuring a first mixer of the plurality of mixers to operate in a six-phase operating mode to reduce the distortions of the RF system, and configuring a second mixer of the plurality of mixers to operate in a three-phase operating mode to reduce power consumption of the RF system.

Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

A receiver includes a switch network, a mixer, and an IQ mismatch (IQMM) estimation circuit. The switch network is adapted to be coupled to an output of a transmitter. The switch network is configured to selectably swap complementary signals of a differential pair. The mixer is coupled to the switch network and is configured to down-convert an output signal of the switch network. The IQ IQMM estimation circuit is coupled to the mixer, and is configured to estimate an IQMM of the transmitter based on an output signal of the mixer.

A receiver includes a switch network, a mixer, and an IQ mismatch (IQMM) estimation circuit. The switch network is adapted to be coupled to an output of a transmitter. The switch network is configured to selectably swap complementary signals of a differential pair. The mixer is coupled to the switch network and is configured to down-convert an output signal of the switch network. The IQ IQMM estimation circuit is coupled to the mixer, and is configured to estimate an IQMM of the transmitter based on an output signal of the mixer.