A power supply circuit in a wireless communications system includes an envelope tracking modulator coupled to a first power amplifier circuit and a second power amplifier circuit, so that the power supply circuit supplies power to the first power amplifier circuit and the second power amplifier circuit. When a transmit signal output by a processor is within a first bandwidth range, the power supply circuit supplies power to the first power amplifier circuit, and the first power amplifier circuit amplifies power of the transmit signal. When the transmit signal output by the processor meets a second bandwidth range, the power supply circuit supplies power to the second power amplifier circuit, and the second power amplifier circuit amplifies the transmit signal.

Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.

Envelope tracking systems for power amplifiers are provided herein. In certain embodiments, an envelope tracker is provided for a power amplifier that amplifies an RF signal. The envelope tracker includes an error amplifier that controls a voltage level of a power amplifier supply voltage of the power amplifier based on amplifying a difference between a reference signal and an envelope signal indicating an envelope of the RF signal. The envelope tracker further includes a multi-level switching circuit that generates an error amplifier supply voltage based on sensing a current of the error amplifier, and uses the error amplifier supply voltage to power the error amplifier.

A radio frequency front end circuit for a multimode transceiver has a first operating mode transmit input port, a second operating mode transmit input/receive output port, and a hybrid first and second operating mode receive output port. A first switch network has one or more switch elements together selectively connecting the first operating mode transmit input port, the second operating mode transmit input/receive output port, and the hybrid first and second operating mode receive output port to a coexistence filter first port. A second switch network has one or more switch elements that together selectively connect a coexistence filter second port to an antenna port.

Radio frequency (RF) systems with tunable filters are provided herein. In certain embodiments, an RF system includes a first RF processing circuit configured to process a first frequency band of a first communication standard and a second frequency band of a second communication standard. The first frequency band and the second frequency band are close in frequency and/or partially overlapping in frequency. The first RF processing circuit includes a tunable filter for changing the bandwidth of the first RF processing circuit to enhance the robustness of the first RF processing circuit to blocker or jammer signals of a third frequency band.

A radio frequency module includes a module substrate, a power amplifier that amplifies a transmission signal in a middle band group, a low noise amplifier that amplifies a reception signal in the middle band group, and a conductive component that transmits a radio frequency signal in a high band group, wherein the power amplifier is mounted on a main surface of the module substrate, the low noise amplifier is mounted on a main surface of the module substrate, and the conductive component is mounted between the power amplifier and the low noise amplifier on the main surface when the module substrate is viewed in plan.

A low noise amplifier topology can achieve very low noise figure by applying multiple magnetic coupling between gate matching inductors and source degeneration inductor of a field effect transistor. The resulting low noise amplifier has smaller inductors, which can have lower thermal noise contribution, and can maintain good gain and linearity performance. For example, a low noise amplifier includes a first inductor to receive an input; a second inductor coupled to the first inductor in series; a first field effect transistor device whose gate receives a signal from the second inductor; and a third inductor coupled to a source of the first field effect transistor device, where the third inductor is magnetically positively coupled to the first inductor and the second inductor.

Power amplifier systems with DC current reuse across stages are disclosed. In certain embodiments, a mobile device includes a transceiver configured to generate a first radio frequency input signal, and a front end system. The front end system includes a first power amplifier stage configured to amplify the first radio frequency input signal to generate a first radio frequency output signal, and a second power amplifier stage configured to amplify a second radio frequency input signal to generate a second radio frequency output signal. The first power amplifier stage and the second power amplifier stage are electrically connected in a first stack between a first power high supply voltage and a power low supply voltage and configured to operate with a shared DC bias current.

A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.

A transmission/reception baseband-processing device includes a calibration-processing unit configured to correct an input signal input to a transmission unit on the basis of a first characteristic according to characteristics of the transmission unit of a transmission/reception front end-processing unit and a calibration reception unit that is a reception unit of a calibration transmission/reception unit and a second characteristic according to a characteristic of the calibration reception unit.