A physical layer transceiver for a data channel includes receiver circuitry configured to receive signals on the data channel, transmit circuitry configured to transmit signals onto the data channel, and adaptive filter circuitry coupled to the receiver circuitry and the transmit circuitry and configured to filter the data channel by operating on input frequency-domain data samples to output filtered data samples. The adaptive filter circuitry includes error sample generation circuitry configured to generate error samples representing a difference between a target response and the filtered data samples, arithmetic-only circuitry configured to approximate a windowing function to operate on the error samples, and output sample generation circuitry configured to operate on windowed error samples to provide the output filtered data samples. The comparison circuitry may be configured for time-domain operation and may further be configured to transform the error signals into frequency-domain error signals.

A physical layer transceiver for a data channel includes receiver circuitry configured to receive signals on the data channel, transmit circuitry configured to transmit signals onto the data channel, and adaptive filter circuitry coupled to the receiver circuitry and the transmit circuitry and configured to filter the data channel by operating on input frequency-domain data samples to output filtered data samples. The adaptive filter circuitry includes error sample generation circuitry configured to generate error samples representing a difference between a target response and the filtered data samples, arithmetic-only circuitry configured to approximate a windowing function to operate on the error samples, and output sample generation circuitry configured to operate on windowed error samples to provide the output filtered data samples. The comparison circuitry may be configured for time-domain operation and may further be configured to transform the error signals into frequency-domain error signals.

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Systems and methods are provided for use of common mode rejection (CMR) for echo cancellation in uplink communications. A node in a cable network configured for transmitting downstream (DS) signals and receiving upstream (US) signals, may include echo cancelling circuits configured for cancelling echo introduced by the DS signals and/or transmittal of the DS signals, onto US signals and/or US reception path, to facilitate full-duplex (FDX) communications of the DS signals and US signal. The echo cancelling circuits may be configured for operating in the analog domain. The echo cancelling circuits may include an echo cancelling combiner configured for combining two or more upstream signals non-coherently.

Systems and methods are provided for use of common mode rejection (CMR) for echo cancellation in uplink communications. A node in a cable network configured for transmitting downstream (DS) signals and receiving upstream (US) signals, may include echo cancelling circuits configured for cancelling echo introduced by the DS signals and/or transmittal of the DS signals, onto US signals and/or US reception path, to facilitate full-duplex (FDX) communications of the DS signals and US signal. The echo cancelling circuits may be configured for operating in the analog domain. The echo cancelling circuits may include an echo cancelling combiner configured for combining two or more upstream signals non-coherently.

Provided is a technique of power superposition differential data transmission with low radiation noise at low cost and capable of operating at a radio frequency. A differential transmission board superimposes DC power on a differential data signal from a transmission/reception IC and then transmits the signal to a cable, and includes: a first differential transmission line including two wiring patterns; a second differential transmission line including two wiring patterns; two DC transmission lines that transmit the DC power; two capacitor elements that cut off the DC power and pass only the differential data signal; and two inductor elements that cut off a radio-frequency component that is the differential data signal and pass only a DC component, in which the first differential transmission line and the second differential transmission line are connected in series, in which the two capacitor elements are connected in series to the second differential transmission line, in which the second differential transmission line and the DC transmission line are connected via the two inductor elements, and in which a characteristic impedance in a differential mode of the first differential transmission line and a characteristic impedance in the differential mode of the second differential transmission line are substantially equivalent, and a characteristic impedance in an in-phase mode of the second differential transmission line is higher than a characteristic impedance in the in-phase mode of the first differential transmission line.

Provided is a technique of power superposition differential data transmission with low radiation noise at low cost and capable of operating at a radio frequency. A differential transmission board superimposes DC power on a differential data signal from a transmission/reception IC and then transmits the signal to a cable, and includes: a first differential transmission line including two wiring patterns; a second differential transmission line including two wiring patterns; two DC transmission lines that transmit the DC power; two capacitor elements that cut off the DC power and pass only the differential data signal; and two inductor elements that cut off a radio-frequency component that is the differential data signal and pass only a DC component, in which the first differential transmission line and the second differential transmission line are connected in series, in which the two capacitor elements are connected in series to the second differential transmission line, in which the second differential transmission line and the DC transmission line are connected via the two inductor elements, and in which a characteristic impedance in a differential mode of the first differential transmission line and a characteristic impedance in the differential mode of the second differential transmission line are substantially equivalent, and a characteristic impedance in an in-phase mode of the second differential transmission line is higher than a characteristic impedance in the in-phase mode of the first differential transmission line.