A method for switching clock sources is provided. In the method, Precision Time Protocol, PTP, packets are monitored using each of PTP ports which connect to a new grandmaster (401). A frequency and a phase for the PTP port are calculated based on the PTP packets (402). In response to a successful check for the frequency and the phase, the PTP port is added to a candidate list (403). A phase calibration and a phase stability check may be introduced prior to the alternate BMCA.

Aspects of the present disclosure describe a system and method for synchronizing time, frequency, and phase among a plurality of devices.

In at least one embodiment, an active noise cancellation system. The system includes a first controller, a data bus, and a second controller. The first controller receives first information from a plurality of noise sensing devices and second information from an audio system. The first controller employs a time division multiplexing scheme to generate a multiplexed stream of data including the first information and the second information. The data bus transmits the multiplexed stream of data on a single data channel. The second controller receives the multiplexed stream of data on the single data channel and separates the first information from the second information on the multiplexed stream of data to perform ANC functionality.

Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Aspects of the present disclosure describe a system and method for synchronizing time, frequency, and phase among a plurality of devices.

An apparatus and a method for sampling a signal in a wireless communication system that employs a time division duplex (TDD) scheme are provided. According to various embodiments of the present disclosure, a method for a base station being operated in a wireless communication system that employs TDD comprises the steps of: determining a switching section for controlling a conversion mode of a sampling rate conversion circuit based on a timing advance (TA) value with respect to a signal transmitted by a terminal; generating a switching signal within the switching section; changing the conversion mode from a first mode to second mode in response to the switching signal; and changing a sampling rate of a transmission signal or reception signal based on the second mode. As a result, the transmission signal and the reception signal can be prevented from overlapping in the sampling rate conversion circuit that can perform both of up conversion and down conversion, and hardware resources for changing a sampling rate of a signal can be reduced.

A first signal generated from a signal generator may be synchronized with a local clock of a first device at a first time, and sent to a second device, the first signal having a first frequency. A second signal generated from the signal generator may be further synchronized with the local clock of the first device at a second time, the second signal having a second frequency different from the first frequency, and a difference between the second time and the first time being within a predetermined range of a predetermined time difference. The second signal may then be sent to the second device to enable the second device to determine a distance between the first device and the second device based at least in part on a phase difference between the first signal and the second signal.

Disclosed herein include a system and a method of synchronizing a slave device to a signal from a master device based on pulse width analysis. The pulse width analysis is a process to sample the signal at a sampling frequency of the slave device, determine varying pulse widths of the sampled signal, and determine frequency of an embedded master clock signal of the signal based on statistical analysis of the varying pulse widths. Advantageously, performing pulse width analysis allows synchronization of a slave device with the embedded master clock signal in a time and cost efficient manner. In one aspect, determining a frequency of the embedded master clock signal and adjusting an internal clock of the slave device according to the determined frequency is faster and more cost efficient than iteratively adjusting the internal clock based on feedback loop based circuitries.

Aspects of the present disclosure describe a system and method for synchronizing time, frequency, and phase among a plurality of devices.

Disclosed herein include a system and a method of synchronizing a slave device to a signal from a master device based on pulse width analysis. The pulse width analysis is a process to sample the signal at a sampling frequency of the slave device, determine varying pulse widths of the sampled signal, and determine frequency of an embedded master clock signal of the signal based on statistical analysis of the varying pulse widths. Advantageously, performing pulse width analysis allows synchronization of a slave device with the embedded master clock signal in a time and cost efficient manner. In one aspect, determining a frequency of the embedded master clock signal and adjusting an internal clock of the slave device according to the determined frequency is faster and more cost efficient than iteratively adjusting the internal clock based on feedback loop based circuitries.