A first signal generated from a signal generator may be synchronized with a local clock of a first device at a first time, and sent to a second device, the first signal having a first frequency. A second signal generated from the signal generator may be further synchronized with the local clock of the first device at a second time, the second signal having a second frequency different from the first frequency, and a difference between the second time and the first time being within a predetermined range of a predetermined time difference. The second signal may then be sent to the second device to enable the second device to determine a distance between the first device and the second device based at least in part on a phase difference between the first signal and the second signal.

In at least one embodiment, an active noise cancellation system. The system includes a first controller, a data bus, and a second controller. The first controller receives first information from a plurality of noise sensing devices and second information from an audio system. The first controller employs a time division multiplexing scheme to generate a multiplexed stream of data including the first information and the second information. The data bus transmits the multiplexed stream of data on a single data channel. The second controller receives the multiplexed stream of data on the single data channel and separates the first information from the second information on the multiplexed stream of data to perform ANC functionality.

Systems, circuits, and methods for synchronizing devices in the time-domain are provided. A method, according to one implementation, includes determining a round-trip number based on a width of one cycle of a timestamping clock signal. The round-trip number is equal to a plurality of times that a clock signal is to be transmitted in a loop from a timing-leader component to a timing-follower component and back to the timing-leader component. The method also includes utilizing the timestamping clock signal to detect a cumulative time delay that results when the clock signal is transmitted in the loop a number of times equal to the round-trip number. The cumulative time delay is configured to enable synchronization of the timing-follower component with the timing-leader component.

The apparatus may be a user equipment (UE). The apparatus receives a transmission of at least one of a plurality of first synchronization signals. The apparatus receives at least one repeat transmission of the at least one of the plurality of first synchronization signals. In an aspect, the transmission and the at least one repeat transmission are received in a same synchronization signal block.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

A method for switching clock sources is provided. In the method, Precision Time Protocol, PTP, packets are monitored using each of PTP ports which connect to a new grandmaster (401). A frequency and a phase for the PTP port are calculated based on the PTP packets (402). In response to a successful check for the frequency and the phase, the PTP port is added to a candidate list (403). A phase calibration and a phase stability check may be introduced prior to the alternate BMCA.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

Aspects of the present disclosure describe a system and method for synchronizing time, frequency, and phase among a plurality of devices.

Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.