A cross-domain clock synchronization method, device and system and a computer storage medium, which are applied to a cross-domain synchronization network. A Path Calculate Element (PCE) exchanges a clock synchronization type with a controller participating in clock synchronization path calculation to match the clock synchronization type supported by the PCE and the controller; the PCE acquires physical topological information of the cross-domain synchronization network; the PCE acquires synchronization information of synchronization nodes of the cross-domain synchronization network and/or hop number information between the synchronization nodes; the PCE calculates a clock synchronization path of the cross-domain synchronization network according to the physical topological information as well as the synchronization information and/or the hop number information; and the PCE sends the clock synchronization path to the controller according to the physical topological information to enable the controller to send a clock synchronization instruction to synchronization nodes on the clock synchronization path.

Methods, systems, and apparatus for preserving timing domains of different communications types of signals in a telecommunications network are disclosed. In one aspect a network element (NE) includes a receiver configured to receive communications signals of two different communications types. The NE can include a timing analyzer configured to obtain a local reference clock (LRC), detect two different received reference clocks (RRCs) corresponding to the two different communications types, and for each received communications signal, determine a quantized value (QV) based on a difference between the LRC and the RRC. The NE can include a timing generator configured to generate, for the received communications signal, a transmit reference clock (TRC) that is referenced to, but different from, each of the LRC and the QV. The NE can include a transmitter configured to output an output signal based on the received communications signal and the TRC for the received communications signal.

Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.

Apparatus and methods for asynchronous clock mapping are provided herein. In certain configurations, an upstream server of a transport network generates clock difference data indicating a time difference between a server clock signal and a client clock signal, which have an asynchronous timing relationship with respect to one another. The clock difference data is generated with high precision by using one or more time-to-digital converters (TDCs). The clock difference data is included in a transmitted data stream, and is used by a downstream server to recover client information with enhanced accuracy.

Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

An apparatus includes a receiver configured to receive a signal that has traveled an optical transmission line without returning output from an optical transmitting device and synchronize with the optical transmitting device in order to demodulate the signal; a dispersion compensator configured to compensate for wavelength dispersion caused by transmission of the signal; an acquisition circuit configured to acquire a transmitting timing at which the signal has been transmitted from the optical transmitting device; a calculation circuit configured to calculate a transmission time period from the optical transmitting device to the receiver from the transmitting timing and a receiving timing at which the signal has been received with the receiver; and an amount setting circuit configured to adjust a dispersion compensation amount of the dispersion compensator in accordance with the transmission time period.

The invention relates to data networks, and in particular relates to a method and apparatus for forming and processing data units to enable the transfer of clock quality information in data networks. A method of forming a higher order data unit, comprising payload data and overhead data, from a plurality of lower order data units, is disclosed. The payload of the higher order data unit is formed by combining the plurality of lower order data units. The overhead data of the higher order data unit includes clock quality information relating to clocks associated with the plurality of lower order data units. Embodiments provide a way of transporting clock quality information relating to clocks associated with a number of lower order data units within a single higher order data unit, and enables intermediate networks easily to access the clock quality information.

Embodiments of this application provide a link group configuration method and an apparatus. The link group configuration method includes: obtaining, by a first network device, candidate groups to which M physical ports of the first network device belong respectively; obtaining, by the first network device from a second network device, candidate groups to which M physical ports of the second network device belong respectively; and selecting N physical links from M physical links, as a link group between the first network device and the second network device, based on the candidate groups to which the M physical ports of the first network device belong respectively and the candidate groups to which the M physical ports of the second network device belong respectively.

A first synchronization signal for synchronization with a synchronization signal source is acquired from a first signal source. A first signal synchronized with the synchronization signal source is generated based on the first synchronization signal. A second synchronization signal for synchronization with the synchronization signal source is acquired from a second signal source different from the first signal source. A second signal synchronized with the synchronization signal source is generated based on the second synchronization signal. A timing signal synchronized with the synchronization signal source is generated based on the first signal of a synchronization device. A phase difference between the timing signal and the second signal is output. An offset is set so that there is no phase difference between the timing signal and the second signal based on the phase difference.

A synchronization timing loop detection method includes monitoring an active timing reference for a flapping event at a network element, incrementing a counter for each detected flapping event, determining if the counter exceeds a threshold over a predetermined time period, and, if the counter exceeds the threshold, declaring a possible timing loop on the active timing reference. The flapping event can include the active timing reference being active followed by inactive due to synchronization status messaging and one of a logical and physical timing loop on the active timing reference. A synchronization timing loop detection system and a network element for synchronization timing loop detection for the synchronization timing loop detection method are also disclosed.