Patent classifications
H04J3/0679
CONTROLLED SYNCHRONIZATION GROUP SELECTION
Methods, apparatuses, and computer program products for synchronization in a network are provided. One method includes configuring a first node for joining a first synchronization group with a second node on a lowest stratum, receiving at least one synchronization signal comprising information on at least an identity of the second node, and synchronizing the first node to the first synchronization group based on the synchronization signal.
DIRECTED ACYCLIC GRAPH OPTIMIZATION BASED ON TIMING INFORMATION FOR GENERATING OPTIMIZED NETWORK CLOCK
In one embodiment, a method comprises receiving, by a network device, one or more advertisement messages comprising timing information describing a quality of a network clock that is originated by a master clock device at a root of a directed acyclic graph (DAG); the network device executing an objective function for the DAG providing an optimized loopless time topology for the network clock, synchronized to the master clock device, based on the timing information; and the network device attaching to a parent device in the DAG based on the objective function, for optimized generation of the network clock by the network device.
APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
CROSS-DOMAIN CLOCK SYNCHRONIZATION METHOD, DEVICE AND SYSTEM AND COMPUTER STORAGE MEDIUM
A cross-domain clock synchronization method, device and system and a computer storage medium, which are applied to a cross-domain synchronization network. A Path Calculate Element (PCE) exchanges a clock synchronization type with a controller participating in clock synchronization path calculation to match the clock synchronization type supported by the PCE and the controller; the PCE acquires physical topological information of the cross-domain synchronization network; the PCE acquires synchronization information of synchronization nodes of the cross-domain synchronization network and/or hop number information between the synchronization nodes; the PCE calculates a clock synchronization path of the cross-domain synchronization network according to the physical topological information as well as the synchronization information and/or the hop number information; and the PCE sends the clock synchronization path to the controller according to the physical topological information to enable the controller to send a clock synchronization instruction to synchronization nodes on the clock synchronization path.
SYSTEMS AND METHODS FOR SYNCHRONIZING DEVICE CLOCKS
A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.
TIME SYNCHRONIZATION PATH SELECTION DEVICE AND TIME SYNCHRONIZATION PATH SELECTION METHOD
[Problem to be Solved] Optimizing a route of time synchronization in a network including apparatuses with different types of precision classes.
[Solution to the Problem] A time transmission system includes BC nodes 200 with different types of apparatus performances, and multiple routes of PTP packets from GM nodes 101 and 102 to a BC node 220 via the BC node 200 are present. Each BC node 200 located upstream on a route performs notification of performance information indicating its apparatus performance to the BC node 200 located downstream with respect thereto. The BC node 220 includes a determination index calculation unit 11 that calculates a determination index for each route by referencing the performance information notified from the BC nodes 200 located upstream on each route, and a route selection unit 12 that selects a route for transmitting and receiving PTP packets from multiple routes of PTP packets to the BC node 220, based on the calculated determination index for each route.
TIME SYNCHRONIZATION METHOD AND DEVICE, NETWORK NODE DEVICE
There is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.
Controlled synchronization group selection
Methods, apparatuses, and computer program products for synchronization in a network are provided. One method includes configuring a first node for joining a first synchronization group with a second node on a lowest stratum, receiving at least one synchronization signal comprising information on at least an identity of the second node, and synchronizing the first node to the first synchronization group based on the synchronization signal.
Quantum Secure Network Clock Synchronization
A multi-node, quantum communication network for providing quantum-secure time transfer with Damon attack detection is described. The network includes three or more nodes connected via authenticated communication channels forming a closed loop. By determining differences between the local times at as well as the time durations required for photons to travel between the three or more nodes, the network detects a Damon attack, if present. For example, the network imposes a closed loop condition to detect the Damon attack. The network can also use the local time differences and time durations for photon travel between nodes to synchronize the local clocks at the three or more nodes of the network.
Continuance in quality level of an input timing signal
Continuance in quality level of an input timing signal may be provided. Clock source reference timing information may be receive by a first node from a second node as an input. The first node may be downstream from the second node. Then the first node may receive an event message associated with a future event associated with the second node. The first node may then refrain, for a period of time in response to receiving the event message, from switching the input for clock source reference timing information to a source other than the second node.