In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

A data processing method, a related device, and a system are provided. The method executed by a first network device includes receiving PDH frame data; loading the PDH frame data and a stuffing bit into a virtual container to obtain the virtual container that includes the PDH frame data, where the stuffing bit in the virtual container carries information about a clock frequency difference between a clock frequency of the Ethernet and a clock frequency of the PDH frame data; and performing virtual-container PWE3 encapsulation on the virtual container to obtain a virtual-container PWE3 packet. In at least some embodiments, difficulty in recovering the clock frequency of the PDH frame data when the PDH frame data is transmitted in the Ethernet is reduced, clock frequency jitters and drifts caused by the clock frequency recovery are reduced, and user experience is improved.

In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

A data processing method, a related device, and a system are provided. The method executed by a first network device includes receiving PDH frame data; loading the PDH frame data and a stuffing bit into a virtual container to obtain the virtual container that includes the PDH frame data, where the stuffing bit in the virtual container carries information about a clock frequency difference between a clock frequency of the Ethernet and a clock frequency of the PDH frame data; and performing virtual-container PWE3 encapsulation on the virtual container to obtain a virtual-container PWE3 packet. In at least some embodiments, difficulty in recovering the clock frequency of the PDH frame data when the PDH frame data is transmitted in the Ethernet is reduced, clock frequency jitters and drifts caused by the clock frequency recovery are reduced, and user experience is improved.