Patent classifications
H04J3/076
BYTE STUFFING CIRCUIT AND BYTE STUFFING METHOD
A byte stuffing circuit and a byte stuffing method are provided. The byte stuffing method includes: receiving a first data stream and generating a second data stream according to the first data stream, where a first size of the first data stream is N bytes, and a second size of the second data stream is 2N bytes; in response to an Xth byte of the second data stream matching a first flag byte, overwriting the Xth byte with a first stuffing byte, and inserting a second stuffing byte into an (X+1)th byte of the second data stream, where X is a positive integer between 1 and 2N−1; combining a remnant data stream and a first part of the second data stream to generate a third data stream, and configuring a second part of the second data stream as the remnant data stream; and outputting the third data stream.
Frame generating apparatus and frame generating method
A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.
Byte stuffing circuit and byte stuffing method
A byte stuffing circuit and a byte stuffing method are provided. The byte stuffing method includes: receiving a first data stream and generating a second data stream according to the first data stream, where a first size of the first data stream is N bytes, and a second size of the second data stream is 2N bytes; in response to an Xth byte of the second data stream matching a first flag byte, overwriting the Xth byte with a first stuffing byte, and inserting a second stuffing byte into an (X+1)th byte of the second data stream, where X is a positive integer between 1 and 2N−1; combining a remnant data stream and a first part of the second data stream to generate a third data stream, and configuring a second part of the second data stream as the remnant data stream; and outputting the third data stream.
Frame generating apparatus and frame generating method
A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.
Clock data recovery method and device for branch signal in SDH
Disclosed are a method and a device for recovering clock data of a tributary signal in SDH, wherein the method includes that: it is to extract valid data of the signal from a time slot of each tributary in a synchronous digital hierarchy SDH frame, and store into a storage space corresponding to a time slot of each tributary in a cache; it is to recover a clock signal and a readout signal for the time slot of each tributary by means of time division multiplexing; when the readout signal for the time slot of any tributary is valid, it is to read out contents of the data from the storage space corresponding to the time slot of the tributary in the cache, and latch into a latch corresponding to the time slot; the device includes: a data extracting module, a clock recovery circuit and a data recovery module.