A method of communication between a payload and a platform, including providing power to at least one payload via a platform, periodically sending an identification message from the at least one payload to the platform, decoding the identification message with the platform and sending a response message to the at least one payload, requesting access to one or more ethernet busses supplied by the platform, and enabling the one or more ethernet busses.

A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.

A serial communications bus system comprising a plurality of end users arranged to transmit data on a common data bus, each end user provided with a bus arbiter, physically separate from the respective end user, configured to define, for that end user, a cycle of transmission enable intervals whereby the end user may transmit data on the data bus and transmission disable intervals whereby the end user may not transmit data on the data bus.

Systems and methods for limiting functionality of a vehicle are described. In one example, vehicle feature modules may specify vehicle behaviors and vehicle operation is limited according to the specified behaviors. Vehicle actuators may be adjusted to limit vehicle operation according to the specified vehicle behaviors. The vehicle behaviors may apply to powertrain systems, navigation systems, climate control systems, lighting systems and other vehicle systems.

A method is provided for communicating between passive subscribers of a bus system. A first passive subscriber encodes an original static pattern in a first transmit SERDES element and encodes original user data in a time-synchronized manner with the original static pattern in a second transmit SERDES element. The second passive subscriber receives the encoded static pattern and user data, and generates a sampling clock having a first phase offset and a clock synchronous with a transmit-receive clock having a second phase offset, from the encoded static pattern. The second passive subscriber decodes the encoded static pattern using a first receive SERDES element and the encoded user data, using a second receive SERDES element to obtain a receive data word. The first receive SERDES element and the second receive SERDES element are operated based on the sampling clock, and the receive data word is output synchronously with the synchronous clock.

A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

A serial communication system for communicating data over a Controller Area Network (CAN) bus comprises a security slave device located between a first system node and a Controller Area Network (CAN) bus. The system is characterised in that: said security slave device further comprises a tagging means for inserting data indicative of said first node into a Controller Area Network (CAN) frame received from said first node; said system further comprises a security master device, located between said Controller Area Network (CAN) bus and a second system node; said security master device further comprises a means of extracting said data indicative of first said node from a received data frame; and said system further comprises a means of checking the validity of received Controller Area Network (CAN) frame associated to said extracted data indicative of said first node.