A user station for a serial bus system. The user station includes a receiver for receiving a signal from a bus of the bus system, and a device for evaluating the reception signal that is output by the receiver. The receiver generates a digital reception signal from the signal received from the bus and to output the signal to the device at a terminal. The device evaluates the digital reception signal with regard to a predetermined communication protocol that establishes when a predetermined communication phase, which indicates a subsequent transfer of useful data in a message, begins and ends. The device reverses the data flow of the digital reception signal to the receiver at the terminal for a time period of at least one bit if the evaluation of the device shows that data at that time are being received from the bus in the predetermined communication phase.

Two or more modules communicate over a common control network including receiving by a message packet having data defined by a signal level at defined bit quanta of a bit, the defined bit quanta being less than every bit quanta of a bit, and the communication device samples bit quanta other than the defined bit quanta. The module receives signal disturbances and decodes the signal disturbances as having a value different from an expected value of the certain bit. In another form, the module uses a first counter based on a clock local to the communication device and a second counter having a higher sampling rate than the first counter. Here, the module receives over the control network a synchronizing portion of a message and counts clock ticks of the second counter over a portion of the message to determine a clock rate for a module that transmitted the message.

An electric system for transmitting serial communication messages with different priorities over a communication link. The data to be transmitted is arranged in serial communication messages comprising a start of packet (SOP) symbol and data symbols. The ongoing transmission of a first message is interrupted if a SOP symbol of a second message is sent before the first message has been completed. Transmission of the first message is continued only after the second message has been sent.

A transceiver device for a bus system. The transceiver device includes first and second bus terminals for connection to first and second signal line of the bus system, and a transmitting unit for outputting a bus transmission signal to the first and second bus terminals. The transceiver device includes an input connection for receiving a transmission input signal useable for controlling an operating state of the transmitting unit, and a detection device, which to detect the presence of a first predefinable condition and, if the first predefinable condition is present, to interconnect the first and second bus terminals via a predefinable electrical resistance for a predefinable first period of time.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

A transceiver device for a bus system. The transceiver device includes a first bus terminal for connection to a first signal line of the bus system, a second bus terminal for connection to a second signal line of the bus system, and a receiving unit for receiving a bus receive signal from the first and second bus terminals. The transceiver device is designed to interconnect the first and second bus terminals via a predefinable electrical resistance for a predefinable first period of time. The predefinable first period of time is selectable as a function of at least one parameter of the receiving unit.

A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver, wherein the transceiver is configured to determine bit timings from a data frame received by the receiver. The transceiver is further configured to detect attempts to introduce a signal glitch in a predetermined portion of the data frame and upon detection of the signal glitch, the transceiver is configured to invalidate the data frame on a transmission line and/or disable the transmitter for a predetermined period.

A Controller Area Network, CAN, device comprising: a compare module configured to interface with a CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD input interface; an identifier memory configured to store an entry that corresponds to at least one identifier; compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal upon a match; a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message, wherein the signal is output from the TXD output interface to the CAN transceiver; and wherein the signal generated by the signal generator provides for one or more dominant bits that are timed so that at a bit immediately following a FDF field or the FDF field bit is made dominant.

An apparatus for use with a Controller Area Network (“CAN”) transceiver includes a first input for receiving transmit-data and; a second input for receiving receive-data. The transmit-data includes data generated by a CAN controller to cause a CAN transceiver to transmit signalling that represents the transmit-data on the CAN bus and the receive-data indicates signalling from the CAN bus. The apparatus is configured to detect, in the receive-data, one or more fields of a CAN frame. The apparatus is then configured to prevent the CAN transceiver from transmitting the signalling that represents the transmit-data at times corresponding to the detected one or more fields of the CAN frame, thereby preventing an error frame in the transmit-data from being transmitted.

A method is described for serial data transmission in a bus system having at least two participating data processing units, the data processing units exchanging messages via the bus, the sent messages having a logical structure in accordance with CAN standard ISO 11898-1. When a first changeover condition is present, then, deviating from CAN, the data field of the messages can include more than eight bytes, the values of the data length code being interpreted, given the presence of the first changeover condition to determine the size of the data field. For forwarding data between the data field and the application software, at least one buffer memory is provided, and, if the size of the data field differs from the size of the buffer memory used, the forwarded quantity of data is adapted at least corresponding to the difference in size between the data field and the buffer memory.