An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

Accordingly embodiments herein disclose a quarter rate speculative DFE. The quarter rate speculative DFE includes a plurality of sampler circuits connected to an input terminal. The plurality of sampler circuits are configured to sample an input signal into a plurality of data samples in parallel. A plurality of quarter rate look ahead circuit connected to the plurality of sampler circuits. The plurality of quarter rate look ahead circuit is configured to simultaneously perform an align operation and a look ahead operation on the plurality of data samples based on the different clock phases to obtain a plurality of latched outputs. A plurality of multiplexers connected to the plurality of quarter rate look ahead circuit. The plurality of multiplexers is configured to generate two speculative data streams by multiplexing respective correction coefficients of each of the plurality of latched outputs.

A digital interpolation filter delivering a series of output samples approximating a signal x(t) at sampling instants of the form (n+d)T s based on a series of input samples of the signal x(t) taken at sampling instants of the form nT s. Such a filter implements a transfer function in the Z-transform domain, H c<i/>d (Z−1), expressed as a linear combination between: a first transfer function H 1 d<i/>(Z−1) representing a Lagrange polynomial interpolation of the input samples implemented according to a Newton structure (100); and a second transfer function H 2 d (Z−1) representing another polynomial interpolation of the input samples implemented according to another structure comprising at least the Newton structure; the linear combination being a function of at least one real combination parameter c.

There is provided a device comprising a channel equalizer and a monitoring device, wherein the device is configured to establish a point-to-point network connection with a connected device via a network cable, by executing an initial training cycle so data received via the network cable is readable by the device. The channel equalizer is configured to continuously adapt to characteristics of the network cable by continuous training of the channel equalizer to help maintain the network connection, and the monitoring device is configured to monitor signals received from the network cable for out-of-range signals, to temporarily interrupt the continuous training of the channel equalizer when out-of-range signals are detected, and to resume the continuous training once the out-of-range signals are no longer detected without executing the initial training cycle again.

The disclosed embodiments provide a system that implements a low-aperture-delay sampler. The system includes a sampler input, which receives an input signal, and a clock input, which receives a clock signal. The system also includes: a first sampling channel, which samples the input signal when the clock signal is low and is associated with a previous clock phase; and a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase. The system additionally includes a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

The disclosed embodiments provide a system that implements a low-aperture-delay sampler. The system includes a sampler input, which receives an input signal, and a clock input, which receives a clock signal. The system also includes: a first sampling channel, which samples the input signal when the clock signal is low and is associated with a previous clock phase; and a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase. The system additionally includes a combining mechanism, which combines outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

A digital interpolation filter delivering a series of output samples approximating a signal x(t) at sampling instants of the form (n+d)T s based on a series of input samples of the signal x(t) taken at sampling instants of the form nT s. Such a filter implements a transfer function in the Z-transform domain, H c<i/>d (Z−1), expressed as a linear combination between: a first transfer function H 1 d<i/>(Z−1) representing a Lagrange polynomial interpolation of the input samples implemented according to a Newton structure (100); and a second transfer function H 2 d (Z−1) representing another polynomial interpolation of the input samples implemented according to another structure comprising at least the Newton structure; the linear combination being a function of at least one real combination parameter c.

A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.