An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low-frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimate from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate . The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

In accordance with an embodiment the method includes temporarily configuring the vector processor with a new set of vectoring coefficients during one or more selected symbol positions; restoring the current set of vectoring coefficients outside the one or more selected symbol positions; obtaining at least one error measure over respectively at least one line of the group of vectored lines during the one or more selected symbol positions; and determining a suitability indication for the new set of vectoring coefficients based on the obtained at least one error measure.

An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low-frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimate from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

A communication receiving device includes a clock data recovery circuit, an analog-to-digital converter (ADC), a channel evaluating circuit, a first equalizer, and a selector. The clock data recovery circuit is configured to generate a clock signal according to a first digital signal. The ADC is coupled to the clock data recovery circuit, and configured to convert a first analog signal to a second digital signal according to the clock signal. The channel evaluating circuit is configured to analyze the second digital signal to output a selection signal. The first equalizer is coupled to the ADC, and configured to equalize the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer, the ADC, and the clock data recovery circuit. The selector is configured to output the second digital signal or the third digital signal as the first digital signal according to the selection signal.

A waveform correction apparatus includes a receiver configured to receive a first signal and a second signal from a signal transmission apparatus, the first signal being a PAM4 signal having a data pattern of a bit array in which gray coding is performed, and the second signal being a PAM4 signal having a data pattern of a bit array in which the gray coding is not performed, and a processor coupled to the receiver and configured to adjust a number of taps in an equalizer based on a difference between correct count values of forward error correction performed on the respective data patterns of the first signal and the second signal.

A communication receiving device includes a clock data recovery circuit, an analog-to-digital converter (ADC), a channel evaluating circuit, a first equalizer, and a selector. The clock data recovery circuit is configured to generate a clock signal according to a first digital signal. The ADC is coupled to the clock data recovery circuit, and configured to convert a first analog signal to a second digital signal according to the clock signal. The channel evaluating circuit is configured to analyze the second digital signal to output a selection signal. The first equalizer is coupled to the ADC, and configured to equalize the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer, the ADC, and the clock data recovery circuit. The selector is configured to output the second digital signal or the third digital signal as the first digital signal according to the selection signal.

A bus system according to the present disclosure includes: three or more devices that include one or a plurality of imaging devices, and transmit and receive a data signal in a time-division manner; and a bus to which the three or more devices are coupled and through which the data signal is transmitted. A first device of the three or more devices includes: an equalizer having a first operation mode in which a received signal is equalized with use of a coefficient set including one or a plurality of equalization coefficients, a storage unit that stores a plurality of the coefficient sets, and a communication controller that selects one of the plurality of the coefficient sets stored in the storage unit and causes the equalizer to operate in the first operation mode with use of the selected coefficient set.

In accordance with an embodiment the method includes temporarily configuring the vector processor with a new set of vectoring coefficients during one or more selected symbol positions; restoring the current set of vectoring coefficients outside the one or more selected symbol positions; obtaining at least one error measure over respectively at least one line of the group of vectored lines during the one or more selected symbol positions; and determining a suitability indication for the new set of vectoring coefficients based on the obtained at least one error measure.

A bus system according to the present disclosure includes: three or more devices that include one or a plurality of imaging devices, and transmit and receive a data signal in a time-division manner; and a bus to which the three or more devices are coupled and through which the data signal is transmitted. A first device of the three or more devices includes: an equalizer having a first operation mode in which a received signal is equalized with use of a coefficient set including one or a plurality of equalization coefficients, a storage unit that stores a plurality of the coefficient sets, and a communication controller that selects one of the plurality of the coefficient sets stored in the storage unit and causes the equalizer to operate in the first operation mode with use of the selected coefficient set.