An intergrated circuit (IC) chip includes receiver circuitry to receive signals from a second IC chip. The receiver circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate at least one tap weight corresponding to the at least one tap based on edge information of previously received signals.

Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

A signal compensation method and device, where the method includes receiving a signal sequence suffering from intersymbol interference (ISI), setting a first filtering coefficient to perform filter compensation on the received signal sequence to obtain a first compensation signal sequence, setting a balance filtering coefficient to perform filter compensation on the first compensation signal sequence to obtain a balance compensation result, where the balance filtering coefficient is obtained by adjusting, according to a first compensation error, a balance filtering coefficient set last time, performing sequence estimation on the balance compensation result and outputting the balance compensation result, where the first compensation error adjusts the balance filtering coefficient set to perform filter compensation on the first compensation signal sequence in an iterative manner, thereby effectively compensating for the signal sequence suffering from the ISI, and improving performance of an optical fiber communications system.

Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.

A method and apparatus for signal equalization are provided. Multiple decision components are arranged in a sequence, beginning with a history portion and ending with a decode portion. Each decision component performs a decode decision on a symbol. Decode decisions are passed forward to other decision components where they can be used to compensate for intersymbol interference. Decode decision output by the history portion are otherwise discarded, while decode decisions output by the decode portion are output as a decoded signal. In the next decode cycle, input previously provided to the decode portion is again provided to the history portion, in a sliding, overlapping block manner.

A Radio Frequency Impairments (RFI) compensator and a process to remove RFI is disclosed. The RFI compensator including: a conjugator to conjugate a signal {tilde over (x)}[n] to provide a signal {tilde over (x)}*[n]; and a filter to apply coefficients that equalize a linear distortion of the signal {tilde over (x)}[n] and reject an interfering image of the signal {tilde over (x)}*[n]. The signal {tilde over (x)}[n] maybe a single wideband carrier or may include multiple carriers at different carrier frequencies.

A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.