Patent classifications
H04L2025/03745
Channel equalizer and corresponding operating method
In accordance with a first aspect of the present disclosure, a channel equalizer is provided for use in a near field communication (NFC) device, the channel equalizer comprising: a filter configured to receive an input signal and to generate a filtered output signal; an estimator configured to determine filter coefficients to be used by said filter; a synchronizer configured to determine when to enable the channel equalizer and to provide one or more corresponding control signals to the estimator. In accordance with a second aspect of the present disclosure, a corresponding method of operating a channel equalizer for use in a near field communication (NFC) device is conceived.
CHANNEL EQUALIZER AND CORRESPONDING OPERATING METHOD
In accordance with a first aspect of the present disclosure, a channel equalizer is provided for use in a near field communication (NFC) device, the channel equalizer comprising: a filter configured to receive an input signal and to generate a filtered output signal; an estimator configured to determine filter coefficients to be used by said filter; a synchronizer configured to determine when to enable the channel equalizer and to provide one or more corresponding control signals to the estimator. In accordance with a second aspect of the present disclosure, a corresponding method of operating a channel equalizer for use in a near field communication (NFC) device is conceived.
Bi-level adaptive equalizer
At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.
BI-LEVEL ADAPTIVE EQUALIZER
At least some aspects of the present disclosure provide for a method. In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.
Adaptive equalization channel extension retimer link-up methodology
Methods and apparatus for implementing adaptive equalization channel extension retimer link-up in high-speed serial links. Under aspects of the proposed methodology, the retimer device intervenes with the adaptive equalization training, training both ends of the link individually between the two end points, and once both of the retimer's receivers are trained, it propagates the receiver readiness indication through from one end point to the other. This allows all sections of the link to train at the same time, and for all devices to transition to data mode at the same time, once all channels have been adapted to and trained. This methodology also applies to cascaded retimer device configurations, where multiple retimers are being used to extend the channel even further.
ADAPTIVE EQUALIZATION CHANNEL EXTENSION RETIMER LINK-UP METHODOLOGY
Methods and apparatus for implementing adaptive equalization channel extension retimer link-up in high-speed serial links. Under aspects of the proposed methodology, the retimer device intervenes with the adaptive equalization training, training both ends of the link individually between the two end points, and once both of the retimer's receivers are trained, it propagates the receiver readiness indication through from one end point to the other. This allows all sections of the link to train at the same time, and for all devices to transition to data mode at the same time, once all channels have been adapted to and trained. This methodology also applies to cascaded retimer device configurations, where multiple retimers are being used to extend the channel even further.
Equalizer boost setting
One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an equalized output signal over a plurality of time intervals according to a given equalizer setting thereof. The counter provides a count value to represent to a number of times that the equalized output signal crosses each of a plurality of thresholds over the plurality of time intervals. The controller evaluates the count value for each of the plurality of thresholds at each of a plurality of equalizer settings and configures the equalizer setting based on the evaluation of the count values for each of the equalizer settings.
EQUALIZER BOOST SETTING
One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an equalized output signal over a plurality of time intervals according to a given equalizer setting thereof. The counter provides a count value to represent to a number of times that the equalized output signal crosses each of a plurality of thresholds over the plurality of time intervals. The controller evaluates the count value for each of the plurality of thresholds at each of a plurality of equalizer settings and configures the equalizer setting based on the evaluation of the count values for each of the equalizer settings.
Signal receiving device for Ethernet and control method thereof
This invention discloses a signal receiving device for Ethernet and a control method thereof. The signal receiving device includes a gain control circuit, an alien near-end crosstalk canceller, a noise canceller, and a DFE. The gain control circuit adjusts an input signal of the signal receiving device according to a setting parameter. The alien near-end crosstalk canceller cancels an alien near-end crosstalk interference. The noise canceller uses a first filter to cancel noises. The DFE uses a second filter to cancel an inter-symbol interference of the input signal. The method includes steps of: temporarily stopping the gain control circuit from updating the setting parameter before a seed collision occurs, and temporarily stopping one of the noise canceller and the decision feedback canceller from updating the first filter coefficient of the first filter or the second filter coefficient of the second filter temporarily during the seed collision.
Decision feedback equalizers and operating methods thereof
A decision feedback equalizer (DFE) includes a sampler for receiving a first input signal and comparing an amplitude of the first input signal with a first predetermined voltage level and a second predetermined voltage level. The DFE includes a DFE logic circuit for receiving at least one first sign signal based on comparison results, and for selectively updating a tap coefficient based on the at least one first sign signal. The DFE logic circuit is configured to update the tap coefficient when the at least one first sign signal indicates the amplitude of the first input signal is not between the first predetermined voltage level and the second predetermined voltage level. The DFE logic circuit is configured to maintain the tap coefficient when the at least one first sign signal indicates the amplitude of the first input signal is between the first and the second predetermined voltage levels.