A signal transmission circuit element, a multiplexer circuit element and a demultiplexer circuit element are disclosed. The signal transmission circuit element is connected among multiple electronic modules so as to transmit an electrical signal. The signal transmission circuit element includes an input terminal, an input equalizer, an output driver and an output terminal. The input terminal is for inputting an electrical signal to the input equalizer. The output driver is electrically connected to the input equalizer. The output terminal is electrically connected to the output driver so as to output the electrical signal. Accordingly, after the input terminal receives the electrical signal, the input equalizer can perform gain compensation on the electrical signal, and then an output capacitance of the electrical signal is driven by the output driver and outputted through the output terminal.

The present disclosure includes a method of performing synchronization and frequency offset estimation The method includes an input signal corresponding to a single received training sequence. Phase information and a phase index are generated by performing an auto-correlation function (ACF) on the input signal. A templet signal associated with a sample index of the input signal is generated based on at least one pre-stored look-up table (LUT), the phase index, a frequency bandwidth of the input signal, and the sample index. Power associated with the sample index is calculated by performing a matched filtering on the input signal based on the templet signal. A synchronization timing and a frequency offset for the input signal are simultaneously determined based on a result of the matched filtering.

A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.

The present disclosure includes a method of performing synchronization and frequency offset estimation The method includes an input signal corresponding to a single received training sequence. Phase information and a phase index are generated by performing an auto-correlation function (ACF) on the input signal. A templet signal associated with a sample index of the input signal is generated based on at least one pre-stored look-up table (LUT), the phase index, a frequency bandwidth of the input signal, and the sample index. Power associated with the sample index is calculated by performing a matched filtering on the input signal based on the templet signal. A synchronization timing and a frequency offset for the input signal are simultaneously determined based on a result of the matched filtering.

A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.

An apparatus for correcting a deviation between a plurality of transmission channels includes a first transmission channel and a second transmission channel. The apparatus also includes a phase offset unit configured to set a phase offset between the first transmission channel and the second transmission channel such that a phase deviation between the first transmission channel and the second transmission channel deviates from zero, a power detection unit configured to detect signal powers of the first transmission channel and the second transmission channel under the phase offset, a processing unit configured to determine, based on the detected signal powers, a deviation correction value between the first transmission channel and the second transmission channel, where the deviation correction value includes a phase correction value, and a phase correction unit configured to set the phase correction value between the first transmission channel and the second transmission channel.

An apparatus for correcting a deviation between a plurality of transmission channels includes a first transmission channel and a second transmission channel. The apparatus also includes a phase offset unit configured to set a phase offset between the first transmission channel and the second transmission channel such that a phase deviation between the first transmission channel and the second transmission channel deviates from zero, a power detection unit configured to detect signal powers of the first transmission channel and the second transmission channel under the phase offset, a processing unit configured to determine, based on the detected signal powers, a deviation correction value between the first transmission channel and the second transmission channel, where the deviation correction value includes a phase correction value, and a phase correction unit configured to set the phase correction value between the first transmission channel and the second transmission channel.

The present disclosure provides a communication device and a skew correction method thereof. The communication device includes a first signal transceiving device and a correction device. The correction device is coupled to the first signal transceiving device through multiple first channels in a correction mode, each of the first channels has multiple first sub-channels. In the correction mode, the first signal transceiving device simultaneously transmits multiple first data through all the first sub-channels of first channels, and the correction device receives the first data through all the first sub-channels to calculate first skew differences of all the first sub-channels, thus calculating first skew differences according to the first skew values.

An apparatus includes a phase offset unit configured to set a phase offset between the first transmission channel and the second transmission channel such that a phase deviation between the first transmission channel and the second transmission channel deviates from zero, a power detection unit configured to detect signal powers of the first transmission channel and the second transmission channel under the phase offset, a processing unit configured to determine, based on the detected signal powers, a deviation correction value between the first transmission channel and the second transmission channel, where the deviation correction value includes a phase correction value, and a phase correction unit configured to set the phase correction value between the first transmission channel and the second transmission channel.

Examples of wireless OFDM communication systems are described herein which replace pilot subcarriers having known modulation with lower dual subcarriers. At the transmitter, for each resource block, the bits that modulate a few payload subcarriers are selected and then encoded with a short dual code thereby forming dual systematic bits and dual check bits. Such selected payload subcarriers are designated as upper dual subcarriers and the dual check bits modulate the lower dual subcarriers, At the receiver, for each resource block, the dual subcarriers are phase adjusted, demodulated, decoded using the short dual code, and re-modulated thereby forming the original dual subcarrier modulation without phase noise nor channel impairments. The re-modulated dual subcarriers are compared against the received dual subcarriers for channel estimation or carrier phase-locked-loop purposes. For example, prior-art OFDM systems with 4 pilots per resource block could be replaced with 8 dual subcarriers for a rate 1/2 short dual code. An increase in the number of subcarriers used for channel estimation or carrier phase-locked-loop tracking has less error in the channel estimate or phase estimate. Lower error permits lower payload BER, lower transmit power, or wider PLL bandwidth to track higher Doppler frequency shifts.