A three-level encoding transmitter is disclosed in which a transmitter circuit is configured to receive an input data signal including binary data and transmit an encoded data signal. The transmitter circuit can include an inverter circuit configured transmit first and second voltages for each logical level of the binary data. A transmission control circuit can cause the inverter circuit to transmit the voltages or deactivate the inverter circuit based on a first control signal. The transmitter circuit can further include an idle circuit configured to transmit an idle voltage between the first and second voltages when there is no data transmission. The idle circuit may transmit the idle voltage based on a second control signal. The first and second control signals may be configured to only be active when the other is inactive.

A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller. At least one of the first battery cell controller or the second battery cell controller includes at least one encoding/decoding circuit for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique, including modulating the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency, encoding a plurality of data nibbles of the serial data stream into a data packet, the data packet including a plurality of symbols constructed and arranged with at least four consecutive chips per symbol, wherein the at least four consecutive chips per symbol of the data packet includes a DC balanced line code in each of the symbols.

A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels. At least one transceiver is configured in a transmit mode or a receive mode and that discards any combinations of the maximum number of possible combinations to reduce a source of electromagnetic interference (EMI) on the transmission line.

A transmission/reception method and device for isolated communication is proposed. The transmission/reception method includes performing transmission, wherein bit streams are extracted from data and two or more predetermined number of bits are modulated into one DC balanced symbol so as to generate a signal in which a plurality of symbols are listed, thereby transmitting the signal through an isolated communication circuit, and performing reception, wherein the signal is received through the isolated communication circuit and the plurality of symbols included in the signal are demodulated into the two or more predetermined number of bits so as to generate the bit streams and organize the bit streams into the data. The transmission/reception method and device may reduce power consumption at the same communication speed because a plurality of bits is represented by the one DC balanced symbol.

The synthetic circuit 16 synthesizes an offset voltage from an offset voltage generator 14 with a signal output from the other end of the first coil 15 and supplies the synthesized signal to the other end of the second coil 18 through an output matching resistor 17. A potential difference detection unit 21 detects a potential difference between both ends of the output matching resistor 17. A comparison circuit 23 outputs an overcurrent detection signal when a voltage value of a detection signal from the potential difference detection unit 21 exceeds a positive or negative threshold voltage. When the overcurrent detection signal is input, a control unit 24 turns off the switching means 19 and forcibly disconnects the synthetic circuit 16 from the output matching resistor 17.

A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

A waveform shaping circuit is configured without including a diode that is affected by temperature. The waveform shaping circuit includes: a capacitor with one end into which a differential signal Vd0 is inputted and another end connected to an output; an impedance element that has one end connected to the other end of the capacitor and another end into which a target constant voltage is applied; a switch circuit that is constructed of a series circuit with an impedance element and a switch without including a diode, has one end connected to the output, and has another end into which the target constant voltage is applied; and a switch control circuit that shifts the switch into an on state during a low voltage period in an AC component of the differential signal and shifts the switch to an off state during a high voltage period of the AC component.

A waveform shaping circuit is configured without including a diode that is affected by temperature. The waveform shaping circuit includes: a capacitor with one end into which a differential signal Vd0 is inputted and another end connected to an output; an impedance element that has one end connected to the other end of the capacitor and another end into which a target constant voltage is applied; a switch circuit that is constructed of a series circuit with an impedance element and a switch without including a diode, has one end connected to the output, and has another end into which the target constant voltage is applied; and a switch control circuit that shifts the switch into an on state during a low voltage period in an AC component of the differential signal and shifts the switch to an off state during a high voltage period of the AC component.

A waveform shaping circuit includes a capacitor, an impedance element, a switch circuit, and a switch control circuit. Opposite ends of the capacitor are connected to the input and output, respectively. One end of the impedance element supplies a target constant voltage to the output end of the capacitor. The switch circuit has a switch without a diode. When on, the switch applies the target constant voltage to the output. When off, it does not. The switch control circuit switches the switch on during a high voltage period in an AC component of an input pulse signal and switches the switch off during a low voltage period of the AC component. The circuit shapes the input pulse signal into an output pulse signal whose peak-to-peak voltage is equivalent to a peak-to-peak voltage of the AC component and whose voltage during the high voltage period is at the target constant voltage.

A waveform shaping circuit includes a capacitor, an impedance element, a switch circuit, and a switch control circuit. Opposite ends of the capacitor are connected to the input and output, respectively. One end of the impedance element supplies a target constant voltage to the output end of the capacitor. The switch circuit has a switch without a diode. When on, the switch applies the target constant voltage to the output. When off, it does not. The switch control circuit switches the switch on during a high voltage period in an AC component of an input pulse signal and switches the switch off during a low voltage period of the AC component. The circuit shapes the input pulse signal into an output pulse signal whose peak-to-peak voltage is equivalent to a peak-to-peak voltage of the AC component and whose voltage during the high voltage period is at the target constant voltage.