Provided is a reception circuit that suppresses skew of a waveform of a signal and enables high-speed data communication.

A reception circuit according to the present disclosure includes: a first differential stage that receives a first input signal and a second input signal at a first input unit and a second input unit, respectively, and causes first and second currents corresponding to the first and second input signals, respectively, to flow; a second differential stage including a first current path that generates and outputs a first amplified signal corresponding to the first current and a second current path that generates and outputs a second amplified signal corresponding to the second current; a power supply line that supplies power to the first and second differential stages; and at least one variable resistance unit provided in the first or second current path.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information.

A bidirectional isolated communication circuit and method for a differential signal. The circuit comprises a first detection circuit used for receiving a first differential pair from a first direction, converting the first differential pair into a first level signal, and inhibiting common-mode interference; a second detection circuit used for receiving a second differential pair from a second direction, converting the second differential pair into a second level signal, and inhibiting common-mode interference; an isolation adjustment circuit used for being provided between the first detection circuit and the second detection circuit and performing communication isolation; and a watchdog circuit used for being awoken according to the first differential pair and/or the second differential pair, and enabling the bidirectional isolated communication circuit to enter from a small current working mode to a normal working mode to perform communication isolation.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.

According to one embodiment, in a semiconductor integrated circuit, a sampler is connected to an output node of a summer circuit. A shift register is connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3. To a control circuit, output nodes of respective registers of N-th to M-th stages among the K stages of registers are connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K. A first switch includes one end connected to the output node of the summer circuit. A correction circuit includes a first control node that is connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is connected.

An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.