A transmission apparatus (10) according to the present disclosure incudes: a correction value calculation unit (130) configured to calculate a correction value for correcting an initial standby time of a direct wave signal or an indirect wave signal based on a reception time of the direct wave signal and a reception time of the indirect wave signal that follows the direct wave signal, and a transmission time fluctuation compensation unit (140) configured to calculate the standby time by correcting the initial standby time using the correction value and cause the direct wave signal or the indirect wave signal to stand by in accordance with the standby time. The correction value calculation unit (130) calculates a correction value for increasing the standby time of the direct wave signal or reducing the standby time of the indirect wave signal.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

A receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

A method of realization of adaptive equalization and an adaptive equalizer. The adaptive equalizer comprises an equalizer unit, which is used for equaling an input signal according to a compensation coefficient to obtain an output signal; a sampling comparison unit, which is connected to an output of the equalizer and is used for sampling a comparison result of the output signal of the equalizer and a reference voltage corresponding to reference voltage step; a data processing unit, which is connected to the sampling comparison unit and the equalizer unit. It is used for scanning a reference voltage step to determine range of the reference voltage steps to which step the amplitude of the output signal is corresponding; and scanning a compensation coefficient step, and determining the compensation coefficient for equalization according to the range of reference voltage steps. The solution of the present invention resolves such problems as long adaptive adjustment time, algorithm complex and large power consumption of the existing self-adaptive equalization algorithm.

A feed forward equalizer including a first set of filter taps having a first set of filter tap coefficients to be adapted and a second set of one or more filter taps having one or more filter tap coefficients to be constrained. The feed forward equalizer includes an adaptation component to determine a set of adapted filter tap coefficient values corresponding to the first set of filter tap coefficients and a constraint function component to determine a constrained filter tap coefficient value for the second set of the one or more filter taps having the one or more filter tap coefficients to be constrained using a constraint function based on at least a portion of the set of adapted filter tap coefficient values. The feed forward equalizer generates, based at least in part on the constrained filter tap coefficient value, an equalized signal including a set of estimated symbol values.

Millimeter-wave (mmWave) and sub-mmWave technology, apparatuses, and methods that relate to transceivers and receivers for wireless communications are described. The various aspects include an apparatus of a communication device including one or more antennas configured to receive an RF signal and an ADC system. The ADC system includes a 1-bit ADC configured to receive the RF signal, and an ADC controller circuitry configured to measure a number of positive samples in the received RF signal for a plurality of thresholds of the 1-bit ADC, estimate receive signal power associated with the received RF signal based on the measured number of positive samples, determine a direct current(DC) offset in the received RF signal using the estimated received signal power, and adjust the received RF signal based on the determined DC offset.

A method and apparatus are provided in which a set of reference signals is received (2102), and a set of channel signatures for a multiple antenna communication channel is estimated (2104). Channel state information including a set of quality metrics is calculated (2106). In response to the set of quality metrics satisfying a criterion, the baseline receiver for the multiple antenna communication channel is selected (2108). In response to the set of quality metrics not satisfying the criterion, the alternative receiver for the multiple antenna communication channel is selected (2110). The selectable alternative receiver for the multiple antenna communication channel at the user equipment is based on a set of integer linear combinations, where each integer linear combination is based on at least a pair of channel signatures from the estimated set of channel signatures (2112).

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.