Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. In embodiment, a single-ended receiver trains DFE coefficients and the slicer reference voltage to improve the received eye height. The process for training avoids many whole range sweeps thereby shortening training time. A custom data pattern that includes low-frequency (DC with respect to DFE) and high-frequency (AC with respect to DFE) worst cases is used for training in a closed loop manner. Negative DFE is used to measure the AC height of the data. Positive DFE is used to find the DC height of the data pattern.

An information handling system includes a memory subsystem and a basic/input out system (BIOS). The BIOS performs multiple trainings of the memory subsystem, and each of the trainings is performed at a different temperature. The BIOS stores multiple derating values in a derating table of the BIOS, and each of the derating values corresponds to a respective tap value at a respective temperature. During a subsequent power on self test of the information handling system, the BIOS performs a first training of the memory subsystem, and stores a first set of tap values. During a runtime of the information handling system, a memory controller determines whether a temperature of the information handling system has changed by a predetermined amount. In response to the temperature changing by the predetermined amount, the memory controller utilizes the derating values in the derating table to automatically update the tap values.

Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

Systems, apparatus and methods are provided for loopback testing techniques for memory controllers. A memory controller that may comprise loopback testing circuitry that may comprise a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to an output of the inverter and a second input coupled to a second data output from the memory controller.

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

A receiver for cancelling strong signals from combined weak and strong signals includes: a first circuitry for inputting a weak and strong signal as an input; a parametric cancellation circuit for inputting a representation of the strong signal and an output of the first circuitry to produce a cancellation signal; a second circuitry electrically coupled to the parametric cancellation circuit for inputting the cancellation signal to produce a modulated output; a demodulator electronically coupled to the second circuitry for demodulating the modulated output to produce a demodulated output and an error signal, where the demodulated output is the data contained in the weak signal; and an adaptation logic circuit for inputting the representation of the strong signal, the demodulated output and the error signal to adaptively produce parameters for the parametric cancellation circuit. The parametric cancellation circuit further inputs the error signal and the parameters to produce the cancellation signal.

A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.