A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.

The present disclosure provides a method and an apparatus for self-interference cancellation, a terminal and a base station are disclosed. The method includes truncating a signal based on a detection window, where the signal comprises a receive signal and a self-interference signal which is associated with a transmit signal, and a length of the detection window is less than a symbol length, performing self-interference channel estimation to obtain an estimation of a self-interference channel, based on the truncated signal and a first reference signal which is carried by the transmit signal and used for self-interference channel estimation, where the first reference signal has a comb structure in frequency domain, and performing self-interference cancellation based on the transmit signal and the estimation of the self-interference channel. The method can reduce the influence on the accuracy of self-interference channel estimation due to inter-symbol interference caused by timing misalignment. And, the present disclosure provides a method and device for transmitting a first physical signal in a wireless communication system, the method including: mapping a sequence of each antenna port for the first physical signal to a same plurality of subcarriers on same one or more OFDM symbols based on a frequency-domain mapping pattern of the first physical signal; and transmitting the first physical signal.

A receiver includes an interface configured to receive a data signal based on an n-level pulse amplitude modulation (PAM-n) in which n is an integer equal to or greater than 4. The interface may include an analog-digital converting circuit configured to adjust a reference voltage, for distinguishing second bit data from the data signal in a second section, based on first bit data converted from the data signal in a first section and the first bit data converted from the data signal in the second section, the second section being after the first section.

A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.

A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

Examples relate to a transmit apparatus, a receive apparatus, a method for transmitting, a method for receiving and computer readable storage media for transmitting and/or receiving in a communication network. A transmit apparatus for transmitting discontinuous time-frequency operation, DTFO, signals in a communication network comprises a transmitter configured to transmit a DTFO signal comprising monitoring symbols and regular DTFO symbols in the communication network. The apparatus further comprises processing circuitry, which is coupled to the transmitter and configured to generate at least one monitoring symbol for transmission by the transmitter if a time gap of the DTFO signal between two sub-sequent regular DTFO symbols exceeds a first time threshold, wherein the at least one monitoring symbol is configured to enable frequency-domain equalizer, FEQ, adjustment at a receiver of the DTFO signal; and generate a training sequence for transmission by the transmitter if a time period between a last transmission of a monitoring or regular DTFO symbol and a sub-sequent transmission of a DTFO symbol exceeds a second time threshold, the training sequence comprising at least one monitoring symbol preceding a regular DTFO symbol.