Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

A decision-feedback equalizer (DFE) includes a combining circuit and a feedback filter. The combining circuit combines an input signal and at least one feedback signal to generate an equalized signal. The feedback filter generates the at least one feedback signal according to the equalized signal, and includes a controllable delay circuit. The controllable delay circuit receives an output signal that is derived from the equalized signal, and applies at least one delay amount to generate at least one delay signal, wherein the at least one feedback signal is derived from the at least one delay signal.

Circuits, methods and systems that are to be used for dynamically modulating a high frequency bit duration of data based on a status of one or more previous transmitted bits. One circuit comprises a first data path comprising a first input, a first buffer, and a first output connected to a first multiplexer data input. The circuit further comprises a second data path comprising a second input, a second buffer, a phase interpolator, and a second output coupled to a second multiplexer data input. The circuit further comprises a multiplexer having at least two data inputs, at least one control input, and a common output coupled to a transmitter signal line and wherein the at least one control input is operatively coupled to a generated control signal that is based on the status of one or more previous transmitted bits.

Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

Transmitting device for a wireless communication system and method therein for transmitting data. The transmitting device comprises a processor, configured to: obtain a channel response (h); determine pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2) of a pre-processor structure, based on the obtained channel response (h); and pre-process the data, based on the pre-processor structure and the determined pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2). The transmitting device comprises a transmitter, configured to transmit the pre-processed data.

Transmitting device for a wireless communication system and method therein for transmitting data. The transmitting device comprises a processor, configured to: obtain a channel response (h); determine pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2) of a pre-processor structure, based on the obtained channel response (h); and pre-process the data, based on the pre-processor structure and the determined pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2). The transmitting device comprises a transmitter, configured to transmit the pre-processed data.

A serial data channel includes a transmitter that encodes data using a PAM-4 where each symbol is represented by one of four signal levels comprising two balanced pairs of differential signal levels, and a de-emphasis circuit. The circuit determines that a symbol represents as a first instance of a first signal state, determines that a next symbol represents a second instance of the first state, and determines that a third symbol is represented as a second state. The circuit determines that the second state is of a same balanced pair as the first state and, in response, provides a de-emphasis to the second symbol. The circuit determines that the second state is of a different balanced pair as the first state and, in response, provides the de-emphasis and a correction factor to the second symbol.