Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

Embodiments are directed to continuous time linear equalization including a low frequency equalization circuit which maintains DC gain. A first all-pass filter is coupled to an integrated filter, the integrated filter having a low-pass filter and a second all-pass filter. A high-pass filter is coupled to the first all-pass filter and the integrated filter, a differential input terminal being coupled to the first all-pass filter, the integrated filter, and the high-pass filter, where a differential output terminal is coupled to the high-pass filter.

Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.

Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

Signals sent to a memory component are received by circuitry included in the memory component. The circuitry comprises a comparator circuit to process the received signals. The circuitry further comprises a resistor-capacitor (RC) circuit coupled to the comparator circuit to increase bandwidth and reduce interference in the received signals processed by the comparator circuit.

A method and apparatus for processing or generating a high-frequency signal using parallel and undersampled baseband signal processing in the frequency domain.