A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber. The host device IC includes: a parallel-to-serial converter that produces a digital symbol stream; a digital to analog converter that supplies an analog signal to the short-reach link; and a pre-equalizer coupling the parallel-to-serial converter to the digital-to-analog converter, the pre-equalizer filtering the digital symbol stream to at least partly compensate for a channel response of a combined channel that includes the short-reach link, the CTLE, the driver, and the photoemitter.

An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

A method of determining filter coefficients of an equalizer circuit for equalizing a non-linear electronic system is described. The equalizer circuit includes a Volterra filter circuit. Further, an equalizer circuit for equalizing a non-linear electronic system and an electronic device are described.

Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber. The host device IC includes: a parallel-to-serial converter that produces a digital symbol stream; a digital to analog converter that supplies an analog signal to the short-reach link; and a pre-equalizer coupling the parallel-to-serial converter to the digital-to-analog converter, the pre-equalizer filtering the digital symbol stream to at least partly compensate for a channel response of a combined channel that includes the short-reach link, the CTLE, the driver, and the photoemitter.

Embodiments are disclosed for facilitating an end-to-end link channel with one or more lookup tables for equalization. An example system includes a first transceiver and a second transceiver. The first transceiver includes a clock data recovery (CDR) circuit configured to receive communication data from a switch and to manage a lookup table associated with equalization of the communication data. The first transceiver also includes a first driver circuit communicatively coupled to the CDR circuit and configured to generate an electrical signal associated with the communication data. The second transceiver includes a second driver circuit, communicatively coupled to the first transceiver, that is configured to receive the electrical signal from the first transceiver and to modulate a laser source based on the electrical signal to generate an optical signal via the laser source.

Embodiments are disclosed for facilitating an end-to-end link channel with one or more lookup tables for equalization. An example system includes a first transceiver and a second transceiver. The first transceiver includes a clock data recovery (CDR) circuit configured to receive communication data from a switch and to manage a lookup table associated with equalization of the communication data. The first transceiver also includes a first driver circuit communicatively coupled to the CDR circuit and configured to generate an electrical signal associated with the communication data. The second transceiver includes a second driver circuit, communicatively coupled to the first transceiver, that is configured to receive the electrical signal from the first transceiver and to modulate a laser source based on the electrical signal to generate an optical signal via the laser source.

A receiver and method for compensating for linear impairments at a receiver including receiving an Rx signal including an asymmetric response of a satellite filter; pre-equalizing the Rx signal with a coefficient; and demodulating, after the pre-equalizing, the Rx signal.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

A communication system including a transmitter and a receiver is disclosed. The transmitter transmits frames, at least two consecutive frames containing different training sequences. The receiver receives data communicated from the transmitter over a channel. The receiver combines and jointly processes the at least two consecutive frames transmitted by the transmitter to estimate a channel state of the channel.