An information handling system includes a memory subsystem and a basic/input out system (BIOS). The BIOS performs multiple trainings of the memory subsystem, and each of the trainings is performed at a different temperature. The BIOS stores multiple derating values in a derating table of the BIOS, and each of the derating values corresponds to a respective tap value at a respective temperature. During a subsequent power on self test of the information handling system, the BIOS performs a first training of the memory subsystem, and stores a first set of tap values. During a runtime of the information handling system, a memory controller determines whether a temperature of the information handling system has changed by a predetermined amount. In response to the temperature changing by the predetermined amount, the memory controller utilizes the derating values in the derating table to automatically update the tap values.

A system comprising a processing circuitry configured to: obtain a first ordered sequence of symbols associated with a corresponding second ordered sequence of transmitted symbols and including one or more errors, the errors being discrepancies between given symbols of the first ordered sequence and corresponding symbols of the second ordered sequence; determine, for each symbol of the first ordered sequence of symbols, an estimated transmitted symbol, utilizing a Decision Feedback Equalizer (DFE); and determine if the estimated transmitted symbol of a given symbol of the first ordered sequence of symbols, satisfies a saturation threshold condition; and determine an error hypothesis identifying one or more of the errors by comparing the estimated transmitted symbol of at least one symbol of the first ordered sequence of symbols with one or more pairs of thresholds.

A communication quality estimating device estimates an error rate of a signal with FEC capable of correcting K errors. The device obtains a frequency measurement value that indicates a frequency at which a codeword including m errors is received. The device determines a transition probability and a continuation probability included in each of a plurality of formulae, such that a frequency calculation value that is calculated using the plurality of formulae and indicates a frequency at which a codeword including m errors is received is brought close to the frequency measurement value. The device calculates a frequency at which a codeword including more than K errors is received, by using the plurality of formulae each with the determined transition probability and the determined continuation probability. The device estimates after-FEC error rate based on a result of the calculation.

A communication system includes: a transmission device including a transmission data generator, a pattern generator, a transmitter, and a control signal receiver, the transmission data generator that is configured to generate transmission data, the pattern generator that is configured to generate an alternate pattern alternating at every lapse of a predetermined time, the transmitter that includes a first equalization circuit and is configured to transmit a transmission signal including the transmission data and the alternate pattern, the first equalization circuit that is configured to adjust equalization characteristics on the basis of first instruction information, and the control signal receiver that is configured to receive the first instruction information; and a reception device including a receiver, a first detector, and a control signal transmitter, the receiver that is configured to receive the transmission signal, the first detector that is configured to detect a frequency component corresponding to the predetermined time of the alternate pattern included in the transmission signal, and the control signal transmitter that is configured to generate the first instruction information on the basis of a result of detection by the first detector and is configured to transmit the first instruction information.

An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

A comparator includes a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit. The first-stage circuit includes a first input circuit and a second input circuit. The first switching circuit is configured to control the conduction of the first input circuit, and the second switching circuit is configured to control the conduction of the second input circuit. The first input circuit is configured to generate a first differential signal in a sampling phase when being switched on. The second input circuit is configured to generate a second differential signal in a sampling phase when being switched on. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.

Providing a reception device and a communication system capable of preventing signal quality degradation and improving signal transmission efficiency in a case where a data signal is transmitted via a transmission line that connects a plurality of transmission devices and a reception device. Provided is a reception device including a compensation circuit and an adjustment circuit. The compensation circuit is connected to a transmission line connected to each of the plurality of transmission devices and compensates a signal transmitted from each of the transmission devices in time division. The adjustment circuit adjusts operation of the compensation circuit, in which the adjustment circuit adjusts the operation of the compensation circuit by using a first adjustment value that adjusts the operation of the compensation circuit and is read from a recording medium storing the first adjustment value.