The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range. The transmission circuit performs signal transmission according to the target frequency signal.

The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range. The transmission circuit performs signal transmission according to the target frequency signal.

To provide a relay device capable of increasing the number of connected nodes in a bus-type network, and a connector providing the relay device. An active-star coupler as the relay device includes a bit width distortion correction circuit and a ringing pulse absorption circuit, corrects bit width distortion in bit units using the bit width distortion correction circuit and absorbs and eliminates ringing pulses in a terminus of a communication frame using the ringing pulse absorption circuit.

Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a t-switch with gate shunting. One aspect is an apparatus including a first differential switch having a control input. The apparatus further includes a second differential switch coupled to the first differential switch, the second differential switch a control input. A shunt capacitor is coupled between a first output and a second output of the first differential switch, and a first input and a second input of the second differential switch. A first shunt switch having a control input, an input, and an output has the input and the output coupled to the control input of the first differential switch. A second shunt switch having a control input, an input, and an output, has the input and the output coupled to the control input of the second differential switch.

Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

Repeaters are described that operate to rapidly transition from low-power standby states to a low frequency signal transmission state. Bandwidth for high-frequency signal transmission is preserved.

Repeaters are described that operate to rapidly transition from low-power standby states to a low frequency signal transmission state. Bandwidth for high-frequency signal transmission is preserved.

Repeaters are described that operate to rapidly transition from low-power standby states to a low frequency signal transmission state. Bandwidth for high-frequency signal transmission is preserved.

Repeaters are described that operate to rapidly transition from low-power standby states to a low frequency signal transmission state. Bandwidth for high-frequency signal transmission is preserved.