The present disclosure is related to an optical encoder which is configured to provide precise coding reference data by feature recognition technology. To apply the present disclosure, it is not necessary to provide particular dense patterns on a working surface. The precise coding reference data can be generated by detecting surface features of the working surface.

A lidar for generating long PPM waveforms receives an initial PPM code element including a number of code elements and a desired maximum sidelobe height; b) generates a two-column lookup table; c) selects a candidate modulation level; d) compares the values of the number of times a code element difference has been observed in the initial PPM code element from the lookup table against the desired maximum sidelobe height; e when a value of the number of times exceeds the desired maximum sidelobe height, discards the selected candidate modulation level, decrements corresponding values in the lookup table and repeats steps c to d; f otherwise, appends the selected candidate modulation level to the end of the initial PPM code element to update the initial PPM code element, and repeats steps c to f N times to generate a PPM waveform of length N.

Duty cycles of pulse width modulation (“PWM”) pulses are determined by measurements taken with respect to an internally generated clock signal. One of these measurements calculates, in a continuous dynamic manner, a ratio of the number of cycles of the internally generated clock signal to one or more cycles of a PWM clock signal utilized as a time base for generation of the PWM pulses. This clock ratio measurement designates how many cycles of the internally generated clock signal will be used to designate a first portion of a duty cycle for each PWM pulse. Another measurement is utilized to determine a fractional portion of a cycle of the internally generated clock signal that will be used to designate a second portion of the duty cycle for each PWM pulse.

A drive system for a BLDC motor having poles implemented by separate coils that are activated in corresponding phases, which comprises a controller for controlling the level and phase of input voltages supplied to the separate coils; a controlled inverter with outputs, for applying phase-separated input voltages to each of the separate coils at desired timing for each input voltage, determined by the controller; a power source for feeding power to the controlled inverter; an up/down DC-DC converter for converting the feeding power to the input voltages according to a command signal provided by the controller. The controller is adapted to sample the instantaneous angle of the rotor of the BLDC motor; sample the input voltage input voltage and the current of each phase to obtain the input power P; and for each input voltage, calculate the phase difference value that corresponds to the input power and feeds the phase difference value to the up/down DC-DC converter, thereby causing the up/down DC-DC converter to apply each input voltage to its corresponding coil at a specific timing for obtaining an optimal match between each input voltage and the current that is being built up in the corresponding coil.

A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to encode a rising edge and a falling edge of the input digital signal into different encoded signals; an isolating element coupled to the encoding circuit, and being configured to transmit the encoded signal in an electrical isolation manner; and a decoding circuit configured to receive the encoded signal through the isolating element, and to decode the encoded signal to obtain the rising edge and the falling edge, in order to output an output digital signal consistent with the input digital signal.

An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die. The second semiconductor die includes: a fault detection circuit configured to detect electrical faults in the second semiconductor die; a logic circuit coupled to the fault detection circuit and configured to assert a modulation bypass signal in response to a fault being detected by the fault detection circuit; and modulation masking circuitry configured to force the modulated signal to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal being asserted. The first semiconductor die includes a respective logic circuit sensitive to the modulated signal and configured to detect a condition where the modulated signal has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal in response to the condition being detected.

A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.

An over-the-air computation (AirComp) scheme is proposed for federated edge learning (FEEL) without channel state information (CSI) at the edge devices (EDs) or edge server (ES). The proposed scheme adopts the majority vote (MV) principle and uses pulse-position modulation (PPM) symbols constructed with discrete Fourier transform (DFT)-spread orthogonal frequency division multiplexing (OFDM) (DFT-s-OFDM) as votes from EDs. By taking the delay spread and synchronization errors into account, we show how to eliminate the need for truncated-channel inversion (TCI) at the EDs and detect MV at the ED with a non-coherent detector. The proposed method naturally reduces the peak-to-mean envelope power ratio (PMEPR) of the signal as it inherits the properties of the single-carrier (SC) waveform. An alternative proposed scheme also adopts the majority vote (MV) principle but further defines multiple subcarriers and orthogonal frequency division multiplexing (OFDM) symbols for voting options, which reduces to frequency-shift keying (FSK) over OFDM subcarriers as a special case. Since the votes from EDs are separated on orthogonal resources, the proposed scheme eliminates the need for truncated-channel inversion (TCI) at the EDs and allows the ES to detect MV with a non-coherent detector. We also mitigate the peak-to-mean envelope power ratio (PMEPR) of the synthesized signals by using randomization symbols. Through simulations, we show that the proposed schemes provide high test accuracy in fading channels for both independent and identically distributed (IID) and non-IID data while resulting in lower PMEPR symbols as compared to one-bit broadband digital aggregation (OBDA) with quadrature amplitude modulation (QAM).

This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.