Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

An optical transmission system including an optical transmitter and an optical receiver, wherein the optical transmitter includes a signal coding unit that performs non-linear block coding on an M (M is an integer greater than or equal to 1)-value symbol sequence or a bit sequence input as data information to generate an L (L is an integer greater than or equal to 2, L>M)-value symbol sequence that corresponds to the M-value symbol sequence or the bit sequence in one-to-one correspondence, a digital-to-analog conversion unit that converts the generated L-value symbol sequence to an analog signal, and a modulator that generates an optical modulation signal by performing modulation based on the analog signal, and the optical receiver includes a light receiving unit that receives the optical modulation signal transmitted from the optical transmitter and converts the optical modulation signal to an electrical signal, and a signal decoding unit that restores the M-value symbol sequence or the bit sequence by performing processing that is the reverse of processing performed by the signal coding unit, on the electrical signal.

A system may include multiple electrical components. One electrical component such as an imaging sub-system may be communicatively coupled to another electrical component such as control circuitry for the system. The imaging-subsystem may include transmitter circuitry. The transmitter circuitry can include driver circuitry configured to provide the transmitter circuitry output using a multi-level signaling scheme. To generate the control signals for the driver circuitry, pre-driver combinational logic may precede the serializer circuitry and be coupled to the word data latch circuitry. In such a manner, the generated control signals for different portions of the driver circuitry can be better synchronized with one another, thereby helping improve data EYE margin in the multi-level signal scheme.

A communication quality estimating device estimates an error rate of a signal with FEC capable of correcting K errors. The device obtains a frequency measurement value that indicates a frequency at which a codeword including m errors is received. The device determines a transition probability and a continuation probability included in each of a plurality of formulae, such that a frequency calculation value that is calculated using the plurality of formulae and indicates a frequency at which a codeword including m errors is received is brought close to the frequency measurement value. The device calculates a frequency at which a codeword including more than K errors is received, by using the plurality of formulae each with the determined transition probability and the determined continuation probability. The device estimates after-FEC error rate based on a result of the calculation.

A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.

A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information.

An error rate measuring apparatus that measures whether or not an FEC operation of the device under test is possible based on a comparison result of the signal received from the device under test and a test signal includes an operation unit that sets a codeword length and an FEC symbol length of the FEC corresponding to a communication standard of the device under test, a data comparison unit that compares bit string data obtained by converting the signal received from the device under test with error data to detect an FEC symbol error of each FEC symbol length, a display unit that associates the bit string data of the FEC symbol length as one point with one unit region of a display region and performs color-coding display depending on presence or absence of occurrence of the FEC symbol error by each FEC symbol length.

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.