An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

This application discloses example data encoding methods, data decoding methods, and communication apparatuses. One example data encoding method includes generating M encoding units and distributing the M encoding units to N transmission channels. The M encoding units are obtained by encoding L frames. The M encoding units include at least one first-type unit. A first-type unit of the at least one first-type unit includes a first identifier. The first identifier indicates a start location that is in the first-type unit and that is of a frame header of a first frame in the L frames. M, N, and L are integers greater than or equal to 1.

Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

A first wireless device may receive, from a second wireless device, a transmission associated with an MLC scheme. The MLC scheme may include a plurality of bits with at least one first bit corresponding to a first level of the plurality of bits and at least one second bit corresponding to a second level of the plurality of bits. The at least one first bit may be coded with a first level of complexity, but the at least one second bit may be coded with either the first level of complexity or a second level of complexity, where the first level of complexity may be a higher level of complexity than the second level of complexity. The first wireless device may decode the at least one first bit and the at least one second bit using a decoder having a corresponding level of complexity.

A PAM transceiver configured to process an electrical data signal having at least three states includes an electronic circuit comprising: a data interface configured to connect to a duplex communication channel; a first circuit section connected to the data interface; and a second circuit section connected to the data interface. The first circuit section includes an equalizer for compensating for distortions in the data signal and an interpreter downstream of the equalizer for recognizing symbols. The second circuit section includes a delay unit for time-shifting the data signal and an MMA processor for recognizing a signal phase of the data signal. The first circuit section and the second circuit sections are routed to the MMA processor. The second circuit section has a finite impulse response filter configured to monotonize an impulse response of the communication channel.