A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

A method and an apparatus for envelope shaping of a multi-carrier signal in envelope tracking transmission are disclosed. According to an embodiment, a baseband version of an envelope portion belonging to each of multiple carriers in the multi-carrier signal is positioned such that a frequency spacing between adjacent positioned envelope portions is smaller than that between corresponding adjacent carriers. The positioned envelope portions are combined into a composite envelope. The composite envelope is shaped. The shaped composite envelope is split into baseband versions of shaped envelope portions belonging to the multiple carriers. The baseband version of each shaped envelope portion is repositioned such that a frequency spacing between adjacent repositioned envelope portions is equal to that between corresponding adjacent carriers.

A method and an apparatus for envelope shaping of a multi-carrier signal in envelope tracking transmission are disclosed. According to an embodiment, a baseband version of an envelope portion belonging to each of multiple carriers in the multi-carrier signal is positioned such that a frequency spacing between adjacent positioned envelope portions is smaller than that between corresponding adjacent carriers. The positioned envelope portions are combined into a composite envelope. The composite envelope is shaped. The shaped composite envelope is split into baseband versions of shaped envelope portions belonging to the multiple carriers. The baseband versions of each shaped envelope portion is repositioned such that a frequency spacing between adjacent repositioned envelope portions is equal to that between corresponding adjacent carriers.

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

A transceiver includes a receive circuit configured to receive an incoming signal and recover a reference signal at a reference frequency from the incoming signal. The incoming signal is a wireless packet. A first oscillator generates a signal at a set of predetermined frequencies. A first phase lock loop (PLL) interfaced with the first oscillator. The first PLL is configured to adjust a first oscillator frequency of the first oscillator based on an incoming frequency of the incoming signal using the reference frequency. A transmit circuit includes a second oscillator configured to generate a carrier signal at a predetermined frequency and a modulator configured to modulate data over the carrier signal at the predetermined frequency. The transmit circuit includes a second PLL interfaced with the second oscillator that sets the second oscillator to generate the carrier signal at the predetermined frequency using the reference signal. The transmit circuit transmits the modulated carrier signal.

A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.

A voltage controlled oscillator includes a first inductor; a first variable capacitance unit including a first variable capacitance element having a variable capacitance and a second variable capacitance element having a variable capacitance; a first node configured for application of a first voltage to the first variable capacitance unit; a cross-coupled unit including a first transistor and a second transistor, an output of the first transistor connected to an input of the second transistor; a current source configured to flow a current through the first inductor, the first transistor, and the second transistor; a second variable capacitance unit including a third variable capacitance element having a variable capacitance, and a fourth variable capacitance element having a variable capacitance; and a second node different from the first node configured for application of a second voltage to the second variable capacitance unit.

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

A carrier recovery system for a receiver of a phase-modulated signal N-PSK, the system including a first pre-conditioning circuit of the signal received (S(t)), with the pre-conditioned signal (SP(t)) having a component, non-modulated in phase, at the frequency N.sub.c where .sub.c is the carrier used for the modulation N-PSK, and a carrier regeneration circuit to regenerate two sinusoidal signals in quadrature at the frequency .sub.c, with these signals being phase locked with respect to said non-modulated component in phase of the pre-conditioned signal.