A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A signal shaping device includes: a generation unit to perform plural types of predetermined processes on blocks obtained by dividing plural sequences of bit strings by a predetermined length, and generate a plurality of candidate blocks that are candidates for a shaped block to be transmitted; a calculation unit to calculate, on a candidate-block-by-candidate-block basis, a weight of a one-dimensional modulation symbol when a plurality of bits included in the candidate block are converted into the one-dimensional modulation symbol; a selection unit to select, from among the candidate blocks, the shaped block on a basis of the weight; an addition unit to add, to the shaped block, selection information indicating a selection result; and a symbol mapping unit to generate a one-dimensional modulation signal by converting a plurality of bits included in the shaped block, into the one-dimensional modulation symbol.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Embodiments provide a pre-distortion circuit and apparatus, a method and computer program for pre-distorting, a transmitter, a radio transceiver, a communication device, a mobile transceiver, a base station transceiver and a storage. The pre-distortion circuit (10) is configured for a digital quadrature signal. The pre-distortion circuit (10) comprises a first input (12) for an inphase component of the quadrature signal and a second input (14) for a quadrature component of the quadrature signal. The pre-distortion circuit 10 comprises a signal processing circuit (16) configured to determine whether polarities of the inphase component and quadrature component are equal, and to determine pre-distortion coefficients based on the amplitude of the inphase component, the amplitude of the quadrature component, and based on whether the polarities are equal.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A transmitter includes a processing circuit to generate I level data and Q level data that, when respectively converted to I baseband input and Q baseband input, cause a carrier signal modulated by the I baseband input and the Q baseband input to have a desired edge shape in the time domain. The edge shape includes a low portion, a high portion, and an edge portion between the low portion and the high portion. The edge portion has a desired edge time compatible with the frequency of the carrier signal. The transmitter further includes a digital-to-analog converter (DAC) to convert the I level data to the I baseband input and the Q level data to the Q baseband input, and an in-phase and quadrature (I/Q) modulator to perform I/Q modulation of the carrier signal according to the I baseband input and the Q baseband input.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3.sup.rd-order and 5.sup.th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3.sup.rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.