A method for processing a time synchronization packet is provided. In an embodiment a terminal device receives a time synchronization packet of a first clock source from an external device; receives first indication information from a network device, where the first indication information instructs the terminal device to enter a time synchronization activated state of the first clock source, or the first indication information instructs the terminal device to enter a time synchronization deactivated state of the first clock source; and processes the time synchronization packet of the first clock source based on the first indication information. When a clock source is activated and deactivated, the terminal device processes a time synchronization packet of the clock source in different manners, and signaling indicates whether the clock source is activated or deactivated.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

This disclosure provides a time synchronization packet processing method and apparatus. The method includes: A terminal device receives first indication information, where the first indication information indicates the terminal device to enter an activation state of time synchronization for a first clock source, or the first indication information indicates the terminal device to enter a deactivation state of time synchronization; and processes a time synchronization packet of the first clock source based on the first indication information.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.

A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.

A time synchronization method, a time synchronization sender, a time synchronization receiver and a time synchronization system are provided. The method includes: determining whether at least one parameter causing recalculation of a best master clock (BMC) algorithm changes; in a case where it is determined that the parameter changes, sending a 1588 standard-based Announce message; and in a case where it is determined that the parameter does not change, sending a keep-alive message of the Announce message. In the present disclosure, by distinguishing keep-alive messages from protocol messages, the problem that a CPU system is busy due to the processing of Announce messages is solved, thereby realizing the optimization of the 1588 protocol, and reducing the impact on the CPU.

A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.