Patent classifications
H04L7/0008
AUTOMATIC MULTIMEDIA UPLOAD FOR PUBLISHING DATA AND MULTIMEDIA CONTENT
Disclosed herein is a method and system for utilizing a digital data capture device in conjunction with a Bluetooth (BT) enabled mobile device for publishing data and multimedia content on one or more websites automatically or with minimal user intervention. A client application is provided on the BT enabled mobile device. In the absence of inbuilt BT capability, a BT communication device is provided on the digital data capture device. The BT communication device is paired with the BT enabled mobile device to establish a connection. The client application detects capture of data and multimedia content on the digital data capture device and initiates transfer of the captured data, multimedia content, and associated files. The digital data capture device transfers the captured data, multimedia content, and the associated files to the client application. The client application automatically publishes the transferred data and multimedia content on one or more websites.
TRANSMITTER AND RECEIVER MODULE, COMMUNICATION SYSTEM FOR EXCHANGING ETHERNET FRAMES ON A SINGLE M-LVDS LINE
Examples include a transmitter module, a receiver module and a communication system for exchanging Ethernet Medium Access Control frames on a single M-LVDS line.
Enhanced time resolution for real-time clocks
Enhanced resolution for a real-time clock is implemented, which includes a real-time clock configured to operate at a first time resolution, at least one processing unit configured to operate at a second time resolution, wherein the second time resolution has a higher frequency than the first time resolution, a memory for storing data at a location including data from the real-time clock and the at least one processing unit, an interrupt configured to load information into the memory at the location using the at least one processing unit, the interrupt further configured to operate at a frequency associated with the second time resolution, a timing service configured to read information from the memory at the location, the timing service configured to operate at the second time resolution, and a calibration module configured to re-calibrate the real-time clock.
SYSTEM AND METHOD FOR SPARSE DATA SYNCHRONIZATION AND COMMUNICATION
Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.
Drift detection in timing signal forwarded from memory controller to memory device
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
Tolerant PCS for accurate timestamping in disaggregated network elements and synchronization method
A network element includes a port; and a device with circuitry configured to encode data for communication to a second device via a plurality of physical channels, and utilize one of the plurality of physical channels as a dedicated timing channel with encoding thereon different from encoding on the other plurality of physical channels, and interface encoded data via the plurality of physical channels with the port for transmission and reception with a second device.
EtherCAT Device
An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.
Storage device and storage system including the same
A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
Host communication circuit, client communication circuit, communication system, sound reproducing device and communication method
A host side is adapted to be connected to a client side by means of a clock wire, a selection wire, a first data wire and a second data wire. The host side is configured to transmit a digital selection signal over the selection wire to the client side, the selection signal determining either an audio transmission mode or a client communication mode. Further, the host side is configured to transmit digital audio data of a first channel and a second channel over the first and the second data wire to the client side in the audio transmission mode, and to perform client communication over the first and the second data wire in the client communication mode.
DATA PROTOCOL OVER CLOCK LINE
A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.