A clock determining method includes: when both a second network device and a first network device are synchronous with a reference clock, simulating, by using delay information between the second network device and the first network device and clock frequency information of the second network device, a second virtual clock synchronized with a first virtual clock, where the first virtual clock is used to simulate a clock of the first network device. A clock of the second network device can thus be simulated to perform a subsequent operation by using the simulated clock. For example, the simulated clock may be used to estimate precision time protocol (PTP) message synchronization performance of the second network device. Therefore, the PTP message synchronization performance of the second network device may be pre-determined before a global navigation satellite system (GNSS) fails, to guide network operation and maintenance activities.

A system for efficiently thwarting syn flood DDoS attacks on a target server including a CPU, the system comprising: network controller hardware having steering capability; and a software application to create and to configure initial steering object/s which define a steering configuration of the network controller and monitor at least one opened connection to the server, including updating the steering configuration responsive to establishment of at least one connection to the server, wherein the network controller hardware's steering capability is used to provide a SYN cookie value used for said thwarting, and to send at least one packet, modified, to the packet's source.

Embodiments for delay-induced miscommunication reduction are provided. The embodiment may include capturing data streams transmitted between participants in an A/V exchange; translating, on a sender device prior to transmission to a recipient device, an audio stream within the data streams to text; timestamping, on a sender device prior to transmission to the recipient device, each word in the translated audio stream; transmitting the audio stream and the sender-side translated and timestamped audio stream to the recipient device; translating, on the recipient device, the transmitted audio stream to text; timestamping, on the recipient device, each word in the translated audio stream; determining a lag exists in the A/V exchange based on a comparison of each timestamp for corresponding words on the sender-side translated and timestamped audio stream and the recipient-side translated and timestamped audio stream; and generating a true transcript of an intended exchange between the participants based on the comparison.

A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.

A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

A short range radio communication device and a method of controlling a short range radio communication device may include a processing circuit configured to: determine a time offset between an initial starting point of operation of a transceiver in accordance with a first frequency hopping sequence and a shifted starting point of operation of the transceiver in accordance with the first frequency hopping sequence so that a first segment of a frequency range is exclusive of a second segment of the frequency range; and control at least one of a controller and a clock circuit to operate the transceiver in accordance with the first frequency hopping sequence at the shifted starting point.

The present invention relates to an input/output signal synchronization method by a radio frequency unit. The input/output signal synchronization method according to the present invention comprises the steps of: generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an operation frequency range of the radio frequency unit; collecting the Tx input signal and a Tx output signal obtained by outputting the input signal through a Tx function block; and synchronizing the Tx input signal and the Tx output signals, based on a result obtained by the collecting.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

A method for logging a wellbore includes positioning a downhole tool having a downhole clock in the wellbore, logging the wellbore with the downhole tool, transmitting a surface signal from a wellbore surface to the downhole tool, and receiving the surface signal at the downhole tool. The method also includes transmitting a downhole signal from the downhole tool to the surface, receiving the downhole signal at the wellbore surface, and determining clock drift based on an arrival time of the surface signal at the downhole tool and an arrival time of the downhole signal at the wellbore surface.