A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.

Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.

The present invention discloses a transceiver apparatus having phase-tracking mechanism. A phase detection circuit of a receiver circuit performs sampling and phase detection on an input data signal according to a sampling clock signal to generate a phase detection result. A proportional gain circuit of the receiver circuit applies a proportional gain operation on the phase detection result to generate a phase adjusting signal. A CDR circuit of the receiver circuit receives a source clock signal to generate the sampling clock signal and performs phase-adjusting according to the phase adjusting signal. The integral gain circuit apples an integral gain operation on the phase detection result to generate a frequency adjusting signal. The source clock generating circuit receives a reference clock signal to generate the source clock signal and perform frequency-adjusting according to the frequency adjusting signal. The transmitter circuit performs signal transmission according to the source clock signal.

In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to N.sup.th data, where N is an even number equal to or greater than 2, and first to N.sup.th multi-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to N.sup.th data that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to N.sup.th multi-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.