A reception apparatus includes a detection unit that detects occurrence of a phase slip in phase estimation values of time-series received symbol data, and determines an inclination of the phase slip, a delay processing unit that generates first received signal data obtained by delaying received signal data obtained from the time-series received symbol data by one symbol time interval, a phase shift unit that generates second received signal data by performing phase shift according to the inclination, only in a period in which one symbol time interval elapses, on only the received signal data of a symbol time at which the occurrence of the phase slip is detected among pieces of the received signal data, and a remainder processing unit that derives a remainder of a difference between the second received signal data and the first received signal data.

Technologies for calibrated network interlink access. In some embodiments, a system can calculate a first communication latency of a first link between a first processing element in a first switch and a second processing element in a second switch, and a second communication latency associated with a second link between the first processing element and a third processing element in a third switch. The system can determine a delta between the first communication latency and the second communication latency, and whether respective clock rates of the first switch, second switch, and third switch have a clock rate variation, to yield a clock rate variation determination. Based on the delta and clock rate variation determination, the system can determine an offset value for synchronizing the first communication latency and second communication latency. Based on the offset value, the system can calibrate traffic over the first link and/or the second link.

In an embodiment, a receiver included in a communications system includes a channel extractor configured to segregate a received signal into a plurality of channel signals, wherein the plurality of channel signals includes a plurality of data signals; and a plurality of decoders electrically coupled to the channel extractor and configured to decode each of the plurality of channel signals into a respective plurality of decoded data beam portions.

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.

In an embodiment, a receiver included in a communications system includes a channel extractor configured to segregate a received signal into a plurality of channel signals, wherein the plurality of channel signals includes a plurality of data signals; and a plurality of decoders electrically coupled to the channel extractor and configured to decode each of the plurality of channel signals into a respective plurality of decoded data beam portions.

This disclosure contributes a Unified Clock which utilizes frequency alignment throughout network nodes for accurate time stamping and direct elimination of nodes residence delays from times originated in Grand Master (GM) and propagated downstream with PTP messages, wherein downstream slave nodes are maintaining local slave time (LST) delayed to the GM time by downstream links delays only and such links delays are estimated separately and added to the LST in order to derive Local Master Time (LMT) corresponding to the GM time.

A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.