A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

A method may include (1) preparing, at a slave device, a request message that identifies an initial time-to-live value, (2) sending the request message to a plurality of candidate master devices, (3) receiving, at the slave device from one of the candidate master devices, a reply message that identifies a number of hops between the slave device and the one of the candidate master devices, (4) receiving, at the slave device from another one of the candidate master devices, another reply message that identifies another number of hops between the slave device and the another one of the candidate master devices, and then (5) synchronizing a clock of the slave device with a clock of the one of the candidate master devices due at least in part to the number of hops being less than the another number of hops. Various other apparatuses, systems, and methods are also disclosed.

A method of estimating a clock frequency offset in a mobile device relative to a clock frequency of a controller within a UWB network comprises (a) determining, for each of a plurality of anchors, an anchor clock frequency offset relative to the controller clock frequency, (b) broadcasting an anchor data packet from each anchor, the anchor data packet including the respective anchor clock frequency offset, (c) receiving at least one anchor data packet at the mobile device, (d) estimating a mobile device clock frequency offset relative to the anchor clock frequency of the anchor from which the at least one anchor data packet was received, and (e) estimating the clock frequency offset in the mobile device based on the estimated mobile device clock frequency offset and the anchor clock frequency offset included in the at least one received anchor data packet. Furthermore, a TDoA-based localization method and a TDoA-based localization system are described.

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF.sub.INV(s). The VLF.sub.INV(S) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.

An information control method and a communications device are provided. The method includes: obtaining first information; and executing at least one of the following operations: determining a first delay according to the first information; determining a second delay according to the first information; determining delay requirement information according to the first information; sending the delay requirement information to a network element in a communications network; sending bridge delay information to a third-party network or a third-party application; executing a first operation when it is determined that a first condition is met; and executing a second operation when it is determined that a second condition is met, where the first information includes at least one of the following: first time information, second time information, clock information of a first clock, and clock information of a second clock.

A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to N.sup.th data, where N is an even number equal to or greater than 2, and first to N.sup.th multi-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to N.sup.th data that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to N.sup.th multi-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

Embodiments of this application disclose a data processing method, which can be applied to a clock synchronization network system. The system can correct, based on a clock frequency error or a time error, a data timestamp of a data packet collected by the system in a time period in which there is no reference clock, so that a corrected system time of the data packet is consistent with a reference time. This improves accuracy of data record.