Patent classifications
H04L7/0054
SYSTEM FOR ANALYSING PASSIVE NETWORK
A system for analyzing a passive network is provided, the system being configured to extend the frequency band with the interpolation function of the low frequency band and the extrapolation function of the high frequency band for S-parameters with limited measurement band, adjust the propagation delay time for the band-extended S-parameter to derive the final band-extended S-parameter, and analyze the time response of the passive network on the basis of the output voltage waveform estimated by performing convolution on the impulse response to the derived final band-extended S-parameter and the input voltage waveform of the passive network, thereby improving the time response performance of the passive network without a complex circuit conversion process, and making it possible to be capable of lightweight structures. Furthermore, it is possible to improve the accuracy of the impulse response by adjusting the propagation delay time removed from the band-limited S-parameter.
DEVICE INCLUDING SINGLE WIRE INTERFACE AND DATA PROCESSING SYSTEM INCLUDING THE SAME
A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
DETECTION SYSTEM, DETECTION DEVICE, AND DETECTION METHOD
A detection system includes: a signal output unit configured to output, to a measurement target, a measurement signal that exhibits a predetermined temporal change; a signal measurement unit configured to measure a response signal, to the measurement signal, from the measurement target; a calculation unit configured to calculate an impulse response of the measurement target, based on a measurement result of the response signal measured by the signal measurement unit; and a detection unit configured to detect abnormality regarding the measurement target, based on the impulse response calculated by the calculation unit.
Costas sequence time-frequency synchronization method based on all-phase spectrum correction
The present invention relates to the field of digital signal processing, and in particular to a Costas sequence time-frequency joint synchronization method based on all-phase spectrum correction. The method improves the defects existing in a discrete frequency spectrum correction algorithm using short-time Fourier transform and sliding correlation. The improvement mainly comprises: the present disclosure provides a solution based on iterative optimization: when an actual frequency offset is an integral multiple of the spectral resolution, a large error can occur, frequency offset correction and time delay correction are carried out on a signal by using an estimated value having a large estimated error, then estimation is carried out again, and the frequency offset of the signal is not a special value by means of an iteration mode.
REDUCED POWER AND AREA EFFICIENT RECEIVER CIRCUITRY
In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
Accurate Timestamp Correction
In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.
HORIZONTAL CENTERING OF SAMPLING POINT USING VERTICAL VERNIER
Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.
Reduced power and area efficient receiver circuitry
In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
MAINTAINING A VIRTUAL TIME OF DAY
Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.
Horizontal centering of sampling point using vertical vernier
Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.