A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

The present invention provides a method for time synchronizing one or more devices in a control network using a first device. The method comprises selecting a first device from information of the topology of the control network. The method further comprises sending a first set of packets to the second device, receiving a first set of delay requests in response to the first set of packets, and sending a first set of delay responses in response to the first set of delay requests. The method further comprises, determining a first set of forward times and first set of backward times. The method further comprises, determining a first minimum forward time and a first minimum backward time. Further the method comprises determining a first correction factor. The method also comprises, applying the first correction factor to a clock provided at the second device and storing the first correction factor.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

A method for reception of a signal by a subscriber of a real-time network. The signal includes a signal clock having a signal clock frequency and the subscriber includes a counter, which has a counter clock with a counter clock frequency and which maps a local time of the subscriber. The method includes sampling the signal with a reception clock of a reception counter of the subscriber, the reception clock being derived from the counter clock, whereby the reception counter maps the local time of the subscriber, adapting a phase position of the reception clock to a phase position of the signal clock when said reception clock is derived from the counter clock, and sampling the signal at a reception clock frequency of the reception counter

Present disclosure describes the techniques for regaining synchronization between the RPD and the PTP server, without resetting RPD, in the event of run time-phase jump experienced at RPD. To do so, said technique discloses identifying a run time phase jump event at a remote Physical device (RPD) and initiating an Upstream Channel Descriptor (UCD) refresh procedure to reconnect the RPD with Precision Time Protocol (PTP) server.

One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.