H04L7/02

Service Processing Method and Apparatus
20230051477 · 2023-02-16 ·

This application provides a service processing method and apparatus. The method includes: A transmitting device generates a plurality of transmission frames, where an i.sup.th frame in the plurality of transmission frames carries first information, the first information is used to indicate an amount of data of a service that is carried in each of t transmission frames, the t transmission frames include an (i−t).sup.th frame to an (i−1).sup.th frame in the plurality of transmission frames, i−t>0, and t≥1; and sends the plurality of transmission frames to a receiving device. A transmission frame carries information about an amount of data of the service that is carried in a transmission frame before the transmission frame.

WIRED COMMUNICATION SYSTEM INCLUDING ASYMMETRICAL PHYSICAL LAYER DEVICES
20230047951 · 2023-02-16 ·

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

WIRED COMMUNICATION SYSTEM INCLUDING ASYMMETRICAL PHYSICAL LAYER DEVICES
20230047951 · 2023-02-16 ·

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

DATA ON CLOCK LANE OF SOURCE SYNCHRONOUS LINKS
20180006797 · 2018-01-04 ·

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

METHOD AND DEVICE FOR SYNCHRONIZNG INPUT/OUTPUT SIGNALS BY RADIO FREQUENCY UNIT IN WIRELESS COMMUNICATION SYSTEM
20180013542 · 2018-01-11 ·

The present invention relates to an input/output signal synchronization method by a radio frequency unit. The input/output signal synchronization method according to the present invention comprises the steps of: generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an operation frequency range of the radio frequency unit; collecting the Tx input signal and a Tx output signal obtained by outputting the input signal through a Tx function block; and synchronizing the Tx input signal and the Tx output signals, based on a result obtained by the collecting.

METHOD AND DEVICE FOR SYNCHRONIZNG INPUT/OUTPUT SIGNALS BY RADIO FREQUENCY UNIT IN WIRELESS COMMUNICATION SYSTEM
20180013542 · 2018-01-11 ·

The present invention relates to an input/output signal synchronization method by a radio frequency unit. The input/output signal synchronization method according to the present invention comprises the steps of: generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an operation frequency range of the radio frequency unit; collecting the Tx input signal and a Tx output signal obtained by outputting the input signal through a Tx function block; and synchronizing the Tx input signal and the Tx output signals, based on a result obtained by the collecting.

Multiphase clock generators with digital calibration
11711200 · 2023-07-25 · ·

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Multiphase clock generators with digital calibration
11711200 · 2023-07-25 · ·

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Skew detection and correction for orthogonal differential vector signaling codes
11716190 · 2023-08-01 · ·

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Skew detection and correction for orthogonal differential vector signaling codes
11716190 · 2023-08-01 · ·

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.