A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information.

Techniques are presented to improve the accuracy of and reduce the time required for calibration of an in-phase/quadrature (I/Q) transmission circuit. A measurement receiver measures the I/Q mismatch, where an RF phase shift is introduced to distinguish between the transmitter and measurement receiver I/Q mismatches. Rather than assuming an amount of introduced phase shift, a measurement is used to estimate the phase shift. This phase estimate is then used to determine and correct the I/Q mismatch in the transmitter and measurement receiver. An iterative process can be used to improve the I/Q correction factors. Using simple signal processing to measure the phase shift during calibration and to perform the image calibration calculations, the phase shifter requirements can be significantly relaxed, resulting in faster design time and reduced design area/cost. This approach results in reduced calibration time, thus contributing to reduced factory production time and enabling faster live mode image calibration.

The present disclosure provides an analytical framework to investigate judicious topology reweighting of radio networks of clocks, when distributed time transfer and synchronization are based on physical layers and subject to the presence of false timing signals. Protagonist clocks exchange timing information pairwise, which is modeled as clocks tending to follow the majority of their neighbors. Antagonist clocks inject false timing signals, thereby, influencing the timing synchronization of (some of) the other protagonist clocks they meet. A class of pursuit-evasion graphical games subject to complete state observations and exploitation of phase noise disturbances, is proposed in designing clock steering protocols for resilient time metrologies that will be immune to erroneous timing signals injected into remote time dissemination networks.

A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

The present application discloses a network card, time synchronization methods and devices, and computer storage media. The network card includes: a crystal oscillator configured to generate a clock pulse signal; a phase-locked loop configured to provide a local clock source for the network card according to the clock pulse signal; and a connector connected with a host. The network card transmits synchronized time information to each of N VMs, which are run on the host, through a shared channel, where N≥2.

One embodiment relates to a transmitting device, a receiving device, and the like for preventing increases in the number of communication links, power consumption, and circuit layout area. The transmitting device includes a high-speed signal generator, a low-speed signal generator, and a signal superimposing unit. The high-speed signal generator generates a high-speed signal having a limited frequency band. The low-speed signal generator generates a low-speed signal having a frequency lower than the frequency band of the high-speed signal. The signal superimposing unit outputs a superimposed signal of the high-speed signal and the low-speed signal. The receiving device includes a signal separator and a recovery unit. The signal separator separates the received signal into the high-speed signal and the low-speed signal. The recovery unit performs frequency tracking based on the separated low-speed signal and performs phase tracking based on the separated high-speed signal.