A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A master device (10) of a drive system (1) transmits identification information of each first period and a first transmission synchronization signal for each first period of a reference period including a plurality of first periods or transmits identification information of each first period, a first transmission synchronization signal, and a second transmission synchronization signal for each first period of the reference period. A first controller (31) adjusts a phase of each first control period such that the first control period is synchronized with a timing associated with a specific first synchronization signal out of a plurality of first synchronization signals which are acquired by reception of the first transmission synchronization signal a plurality of times using the identification information and controls a first power converter. A second controller (32) adjusts a phase of each second control period such that the second control period is synchronized with a timing associated with a specific second synchronization signal out of a plurality of second synchronization signals which are acquired by one of reception of the first transmission synchronization signal a plurality of times and reception of the second transmission synchronization signal a plurality of times using the identification information and controls a second power converter.

A master device (10) of a drive system (1) transmits identification information of each first period and a first transmission synchronization signal for each first period of a reference period including a plurality of first periods or transmits identification information of each first period, a first transmission synchronization signal, and a second transmission synchronization signal for each first period of the reference period. A first controller (31) adjusts a phase of each first control period such that the first control period is synchronized with a timing associated with a specific first synchronization signal out of a plurality of first synchronization signals which are acquired by reception of the first transmission synchronization signal a plurality of times using the identification information and controls a first power converter. A second controller (32) adjusts a phase of each second control period such that the second control period is synchronized with a timing associated with a specific second synchronization signal out of a plurality of second synchronization signals which are acquired by one of reception of the first transmission synchronization signal a plurality of times and reception of the second transmission synchronization signal a plurality of times using the identification information and controls a second power converter.

A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.

A digital television (DTV) receiving system includes an information detector, a resampler, a timing recovery unit, and a carrier recovery unit. The information detector detects a known data sequence which is periodically inserted in a digital television (DTV) signal received from a DTV transmitting system. The resampler resamples the DTV signal at a predetermined resampling rate. The timing recovery unit performs timing recovery on the DTV signal by detecting a timing error from the resampled DTV signal using the detected known data sequence. The carrier recovery unit performs carrier recovery on the resampled DTV signal by estimating a frequency offset value of the resampled DTV signal using the detected known data sequence.

A wireless transmission method and a transceiver for wireless transmission are disclosed. According to this method, information to be transmitted and transmission control information are encoded into packet length information of wireless frames for transmission, wherein the transmission control information is filled into synchronization packets, sequence number packets and data packets, and the information to be transmitted is only filled into the data packets. Specifically, the method includes sequentially polling data for transmission in units of transmission sequences, and longitudinally encoding the information to be transmitted and data check information into the data packets. The transmission sequences are separated and sorted by the synchronization packets and the sequence number packets, and the data packets are sorted by sequence number fields in the transmission sequence.

A wireless transmission method and a transceiver for wireless transmission are disclosed. According to this method, information to be transmitted and transmission control information are encoded into packet length information of wireless frames for transmission, wherein the transmission control information is filled into synchronization packets, sequence number packets and data packets, and the information to be transmitted is only filled into the data packets. Specifically, the method includes sequentially polling data for transmission in units of transmission sequences, and longitudinally encoding the information to be transmitted and data check information into the data packets. The transmission sequences are separated and sorted by the synchronization packets and the sequence number packets, and the data packets are sorted by sequence number fields in the transmission sequence.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.