An information processing device includes a first input interface to receive data transferred in a first transfer mode in which a plurality of elements of the data each belonging to a same line of a plurality of lines are transferred in parallel, a second input interface to receive data transferred in a second transfer mode in which a plurality of elements of the data each belonging to a corresponding one of the plurality of lines are transferred in parallel, a mode selection circuit to change a transfer mode of the data from the second input interface from the second transfer mode to the first transfer mode based on a signal indicating selection of the second input interface, and an output interface to output one of the data from the first input interface and the data from the second input interface.

An information processing apparatus includes a first bus interface to receive first data transferred in a pixel-parallel transfer mode, a second bus interface to receive second data transferred in a line-parallel transfer mode, a selector to select one of the first data transferred in the pixel-parallel transfer mode and the second data transferred in the line-parallel transfer mode, as input data, a transfer switching circuit to switch between the line-parallel transfer mode and the pixel-parallel transfer mode to process the input data according to the switched transfer mode.

A method of using an interface device to interface to a processing unit is disclosed. The interface device and the processing unit are part of a station of a plurality of stations in a sheet processing line. The method involves using the interface device to receive a control signal from an upstream station, and comparing a selection part of the control signal with a reference, the selection part being part of an addressing part of the control signal. If the comparison result is negative, a further control signal is determined from the control signal, which is derived from and differing from the addressing part of the control signal and the interface device outputs the further control signal to a different interface device corresponding to a processing unit of a downstream station. If the comparison result is positive, an instruction signal is sent from the interface device to the processing unit.

An information processing device includes a first input interface to receive data transferred in a first transfer mode in which a plurality of elements of the data each belonging to a same line of a plurality of lines are transferred in parallel, a second input interface to receive data transferred in a second transfer mode in which a plurality of elements of the data each belonging to a corresponding one of the plurality of lines are transferred in parallel, a mode selection circuit to change a transfer mode of the data from the second input interface from the second transfer mode to the first transfer mode based on a signal indicating selection of the second input interface, and an output interface to output one of the data from the first input interface and the data from the second input interface.

A method of using an interface device to interface to a processing unit is disclosed. The interface device and the processing unit are part of a station of a plurality of stations in a sheet processing line. The method involves using the interface device to receive a control signal from an upstream station, and comparing a selection part of the control signal with a reference, the selection part being part of an addressing part of the control signal. If the comparison result is negative, a further control signal is determined from the control signal, which is derived from and differing from the addressing part of the control signal and the interface device outputs the further control signal to a different interface device corresponding to a processing unit of a downstream station. If the comparison result is positive, an instruction signal is sent from the interface device to the processing unit.

An information processing apparatus includes a first bus interface to receive first data transferred in a pixel-parallel transfer mode, a second bus interface to receive second data transferred in a line-parallel transfer mode, a selector to select one of the first data transferred in the pixel-parallel transfer mode and the second data transferred in the line-parallel transfer mode, as input data, a transfer switching circuit to switch between the line-parallel transfer mode and the pixel-parallel transfer mode to process the input data according to the switched transfer mode.