Separately providing a shift register for performing serial-to-parallel conversion on a BD signal and a shift register for performing parallel-to-serial conversion on a bit pattern to generate a PWM signal increases the scale of a circuit for adjusting a writing start position in the scanning direction of a light beam. Therefore, the shift register for performing serial-to-parallel conversion on a BD signal and the shift register for performing parallel-to-serial conversion on a bit pattern to generate a PWM signal are configured as a common register.

A time delay and integration charge coupled device includes an array of pixels and a clock generator. The array of pixels is distributed in a scan direction and a line direction perpendicular to the scan direction in which at least some of the pixels of the array include three or more gates aligned in the scan direction. The clock generator provides clocking signals to transfer charge along the scan direction between two or more pixel groups including two or more pixels adjacent in the scan direction. The clocking signals include phase signals to transfer the charge to an adjacent pixel group along the scan direction at a rate corresponding to the velocity of the target by driving the gates of the two or more pixel groups and generating a common potential well per pixel group for containing charge generated in response to incident illumination.

Separately providing a shift register for performing serial-to-parallel conversion on a BD signal and a shift register for performing parallel-to-serial conversion on a bit pattern to generate a PWM signal increases the scale of a circuit for adjusting a writing start position in the scanning direction of a light beam. Therefore, the shift register for performing serial-to-parallel conversion on a BD signal and the shift register for performing parallel-to-serial conversion on a bit pattern to generate a PWM signal are configured as a common register.

A time delay and integration charge coupled device includes an array of pixels and a clock generator. The array of pixels is distributed in a scan direction and a line direction perpendicular to the scan direction in which at least some of the pixels of the array include three or more gates aligned in the scan direction. The clock generator provides clocking signals to transfer charge along the scan direction between two or more pixel groups including two or more pixels adjacent in the scan direction. The clocking signals include phase signals to transfer the charge to an adjacent pixel group along the scan direction at a rate corresponding to the velocity of the target by driving the gates of the two or more pixel groups and generating a common potential well per pixel group for containing charge generated in response to incident illumination.