A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

Pixel aperture size adjustment in a linear sensor is achieved by applying more negative control voltages to central regions of the pixel's resistive control gate, and applying more positive control voltages to the gate's end portions. These control voltages cause the resistive control gate to generate an electric field that drives photoelectrons generated in a selected portion of the pixel's light sensitive region into a charge accumulation region for subsequent measurement, and drives photoelectrons generated in other portions of the pixel's light sensitive region away from the charge accumulation region for subsequent discard or simultaneous readout. A system utilizes optics to direct light received at different angles or locations from a sample into corresponding different portions of each pixel's light sensitive region. Multiple aperture control electrodes are selectively actuated to collect/measure light received from either narrow or wide ranges of angles or locations, thereby enabling rapid image data adjustment.

A multimode interline charge coupled device having an array of light sensitive pixels, each configured to accumulate photocharge responsive to light incident on the pixel, and a controller configured to allocate a first portion of the pixels to accumulate photocharge responsive to light from a scene during a plurality of exposure periods and allocate a second portion of the pixels to store photocharge accumulated by pixels in the first portion to provide a plurality of images of the scene greater than two.

Pixel aperture size adjustment in a linear sensor is achieved by applying more negative control voltages to central regions of the pixel's resistive control gate, and applying more positive control voltages to the gate's end portions. These control voltages cause the resistive control gate to generate an electric field that drives photoelectrons generated in a selected portion of the pixel's light sensitive region into a charge accumulation region for subsequent measurement, and drives photoelectrons generated in other portions of the pixel's light sensitive region away from the charge accumulation region for subsequent discard or simultaneous readout. A system utilizes optics to direct light received at different angles or locations from a sample into corresponding different portions of each pixel's light sensitive region. Multiple aperture control electrodes are selectively actuated to collect/measure light received from either narrow or wide ranges of angles or locations, thereby enabling rapid image data adjustment.

Pixel aperture size adjustment in a linear sensor is achieved by applying more negative control voltages to central regions of the pixel's resistive control gate, and applying more positive control voltages to the gate's end portions. These control voltages cause the resistive control gate to generate an electric field that drives photoelectrons generated in a selected portion of the pixel's light sensitive region into a charge accumulation region for subsequent measurement, and drives photoelectrons generated in other portions of the pixel's light sensitive region away from the charge accumulation region for subsequent discard or simultaneous readout. A system utilizes optics to direct light received at different angles or locations from a sample into corresponding different portions of each pixel's light sensitive region. Multiple aperture control electrodes are selectively actuated to collect/measure light received from either narrow or wide ranges of angles or locations, thereby enabling rapid image data adjustment.

A multimode interline charge coupled device having an array of light sensitive pixels, each configured to accumulate photocharge responsive to light incident on the pixel, and a controller configured to allocate a first portion of the pixels to accumulate photocharge responsive to light from a scene during a plurality of exposure periods and allocate a second portion of the pixels to store photocharge accumulated by pixels in the first portion to provide a plurality of images of the scene greater than two.