A distributed, parallel, image capture and processing architecture provides significant advantages over prior art systems. A very large array of computational circuits—in some embodiments, matching the size of the pixel array—is distributed around, within, or beneath the pixel array of an image sensor. Each computational circuit is dedicated to, and in some embodiments is physically proximal to, one, two, or more associated pixels. Each computational circuit is operative to perform computations on one, two, or more pixel values generated by its associated pixels. The computational circuits all perform the same operation(s), in parallel. In this manner, a very large number of pixel-level operations are performed in parallel, physically and electrically near the pixels. This obviates the need to transfer very large amounts of pixel data from a pixel array to a CPU/memory, for at least many pixel-level image processing operations, thus alleviating the significant high-speed performance constraints placed on modern image sensors.

A comparison circuit that includes an input sampling capacitor and an image sensor including the same are provided. The comparison circuit includes an amplifier configured to receive a pixel signal and a ramp signal to perform a correlated double sampling operation, a first pixel capacitor connected to the amplifier through a first floating node and configured to transmit the pixel signal, a first ramp capacitor connected to the amplifier through a second floating node and configured to transmit the ramp signal, a second pixel capacitor connected in parallel to the first pixel capacitor, and a second ramp capacitor connected in parallel to the first ramp capacitor, wherein the second pixel capacitor is formed between the first floating node and first peripheral routing lines, and the second ramp capacitor is formed between the second floating node and second peripheral routing lines.

To reduce a circuit scale in a solid-state image sensor that detects an address event. The solid-state image sensor includes a pixel array unit and a drive circuit. In the solid-state image sensor, in the pixel array unit, a logarithmic response pixel that outputs an analog signal proportional to a logarithmic value of an incident light amount and a detection pixel that detects whether or not a change amount of the incident light amount has exceeded a predetermined threshold and outputs a detection signal indicating a detection result are arrayed. Furthermore, in the solid-state image sensor, the drive circuit drives the logarithmic response pixel and the detection pixel to output the analog signal and the detection signal.

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.

Techniques for facilitating readout addressing verification systems and methods are provided. In one example, an imaging device includes a focal plane array (FPA). The FPA includes a detector array. The detector array includes detectors. Each detector is configured to detect electromagnetic radiation. The FPA further includes a readout circuit configured to perform a readout to obtain image data from each of the detectors. The imaging device further includes a processing circuit. The processing circuit is configured to apply, to the FPA, a plurality of control signals associated with a readout of a subset of the detectors. The processing circuit is further configured to generate a verification value based on the plurality of control signals. The processing circuit is further configured to perform a verification of the plurality of control signals based at least on the verification value. Related methods and systems are also provided.

The present disclosure provides an image sensor, which includes: a pixel collection circuit array including a plurality of pixel collection circuits, each pixel collection circuit being configured to monitor a change in a light intensity in a field of view and enter a triggered state when the change in the light intensity meets a predetermined condition; a global control unit configured to reset the pixel collection circuit array when the image sensor is powered on, and control the pixel collection circuit array in a stable initial state to operate; a photo current detection unit configured to determine whether there is the change in the light intensity, and control an operating state of at least one pixel collection circuit in accordance with the detected change in the light intensity; and a reading unit configured to respond to the pixel collection circuit in the triggered state and output corresponding address information.

A method of measuring light intensity comprising exposing a photodiode to light to cause the photodiode to provide a current of a first polarity, supplying said current to an integrator to integrate said current to provide an integrated output voltage, and comparing the output voltage with a threshold voltage. Charge packages of opposite polarity are applied to said first polarity to reset the integration voltage prior to the start of the integration time. At the end of the integration time, the photodiode is disconnected from said integrator and a reference voltage coupled to the integrator input, whilst a resistance is coupled into the circuit until the comparison signal switches. The comparison signal is monitored to measure a time between the end of the integration time and the switching of the comparison signal to provide a measure of a residual voltage.

A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.

A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.

Provided is a pixel array including a plurality of pixels, each of which includes a photodiode configured to generate a photocharge in a frame including a plurality of unit frames, a floating diffusion node configured to receive the photocharge, a first storage capacitor configured to receive and store a first photocharge generated by the photodiode through the floating diffusion node during a first unit accumulation time period in each of the plurality of unit frames, and a second storage capacitor configured to receive and store a second photocharge generated by the photodiode through the floating diffusion node during a second unit accumulation time period in each of the plurality of unit frames.