A distributed, parallel, image capture and processing architecture provides significant advantages over prior art systems. A very large array of computational circuits—in some embodiments, matching the size of the pixel array—is distributed around, within, or beneath the pixel array of an image sensor. Each computational circuit is dedicated to, and in some embodiments is physically proximal to, one, two, or more associated pixels. Each computational circuit is operative to perform computations on one, two, or more pixel values generated by its associated pixels. The computational circuits all perform the same operation(s), in parallel. In this manner, a very large number of pixel-level operations are performed in parallel, physically and electrically near the pixels. This obviates the need to transfer very large amounts of pixel data from a pixel array to a CPU/memory, for at least many pixel-level image processing operations, thus alleviating the significant high-speed performance constraints placed on modern image sensors.

A photoelectric conversion apparatus includes a pixel array having pixels arranged to form rows and columns and column signal lines configured to output noise signals and optical signals of the pixels, a driver configured to drive the pixels so that the optical signal is output following the noise signal from each pixel, A/D converters configured to perform A/D conversion to convert the noise signals output to the column signal lines into noise data and to subsequently perform A/D conversion to covert the optical signals output to the column signal lines into optical data, a data hold circuit, and a transmitter configured to transmit the noise data converted by the A/D converters to the data hold circuit and to subsequently transmit the optical data converted by the A/D converters to the data hold circuit.

A solid state image sensor includes a pixel array, as well as charge-to-voltage converters, reset gates, and amplifiers each shared by a plurality of pixels in the array. The voltage level of the reset gate power supply is set higher than the voltage level of the amplifier power supply. Additionally, charge overflowing from photodetectors in the pixels may be discarded into the charge-to-voltage converters. The image sensor may also include a row scanner configured such that, while scanning a row in the pixel array to read out signals therefrom, the row scanner resets the charge in the photodetectors of the pixels sharing a charge-to-voltage converter with pixels on the readout row. The charge reset is conducted simultaneously with or prior to reading out the signals from the pixels on the readout row.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

In a solid-state imaging device, a first substrate has a plurality of pixels and a plurality of first control signal lines. The plurality of first control signal lines are connected to pixels of each row. The second substrate includes a plurality of second control signal lines and a control circuit. The arrangement of each of the plurality of second control signal lines on the second substrate corresponds to the arrangement of a corresponding one of the plurality of first control signal lines on the first substrate. The connection portion has a plurality of control connections and a plurality of readout connections. Each of the plurality of control connections is connected to one of the plurality of first control signal lines and a corresponding one of the plurality of second control signal lines.

An image sensor includes a plurality of pixels, each pixel including a light sensing structure including first, second and third light sensing elements sequentially stacked on a substrate, the light sensing structure having a first surface adjacent to a readout circuit and a second surface including a light receiving portion between first and second circumferential portions, a first through via on the first circumferential portion, extending from the first surface to connect with the first light sensing element, and configured to transfer charges of the first light sensing element to the readout circuit, and a vertical transfer gate on a second circumferential portion and configured to transfer charges of the second light sensing element to the readout circuit, the first through via and the vertical transfer gate of each pixel being arranged in a 1-shaped or L-shaped pattern in the first and second circumferential portions.

A computational pixel imaging device that includes an array of pixel integrated circuits for event-based detection and imaging. Each pixel may include a digital counter that accumulates a digital number, which indicates whether a change is detected by the pixel. The counter may count in one direction for a portion of an exposure and count in an opposite direction for another portion of the exposure. The imaging device may be configured to collect and transmit key frames at a lower rate, and collect and transmit delta or event frames at a higher rate. The key frames may include a full image of a scene, captured by the pixel array. The delta frames may include sparse data, captured by pixels that have detected meaningful changes in received light intensity. High speed, low transmission bandwidth motion image video can be reconstructed using the key frames and the delta frames.

A solid-state imaging device includes a photoelectric conversion unit, a light shielding unit and a transfer transistor. The photoelectric conversion unit generates charges by photoelectrically converting light. The light shielding unit is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit. The transfer transistor transfers charges generated in the photoelectric conversion unit. During a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor. During a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

Provided are a solid-state imaging device capable of improving image quality of a captured image even if the pixel size is increased, and an electronic device equipped with the solid-state imaging device. A solid-state imaging device is provided that includes: at least two column areas that perform Analog To Digital (AD) conversion of a pixel signal generated by a pixel; a plurality of vertical signal lines that transfers the pixel signal to the column areas; and a free area in which the plurality of vertical signal lines is not wired, in which two of the vertical signal lines facing each other sandwiching the free area are arranged, and lengths of the two vertical signal lines are substantially equal to each other.